[LimeSDR USB] How to activate the loopback on a LimeSDR board?

Petren · 21 May 2025 20:57

Hello,
I am trying to transmit a signal with the LimeSDR USB. Along that, I would like to receive this signal with the Loopback. So periodically, I can compare the phase from two signals generated in two different syncronized devices.
When trying to activate the Loopback, i found some difficulty. I am using the SoapySDR, so I can use Python with more than one devices.

Dealing with the Loopback, I am tried to replicate what the LimeQuickTest does, writing the same registers. However this approach did not work.

Modify_SPI_Reg(sdr, 0x010D, 8, 7, 2) Selects the active path of the RXFE: LNAL path active

Modify_SPI_Reg(sdr, 0x010C, 7, 7, 1) Power control signal for LNA_RFE

Modify_SPI_Reg(sdr, 0x010C, 6, 6, 1) Power control signal for RXFE loopback 1

Modify_SPI_Reg(sdr, 0x010D, 4, 4, 1) Enables the input shorting switch at the input of the loopback 1 (in parallel with LNAL mixer).

Modify_SPI_Reg(sdr, 0x010D, 2, 2, 1) Enables the input shorting switch at the input of the LNAL.

Modify_SPI_Reg(sdr, 0x010D, 1, 1, 1) Enables the input shorting switch at the input of the LNAW.

Modify_SPI_Reg(sdr, 0x0101, 12, 11,1) Controls the loss of the of the loopback path at the TX side

Modify_SPI_Reg(sdr, 0x0103, 10, 10, 1) Enable signal for TXFE, band 2

Modify_SPI_Reg(sdr, 0x0113, 5, 2, 2) Controls RXFE loopback gain
After that I saw on a thread here to write just two registers. As the other try, I did not work.

Modify_SPI_Reg(sdr, 0x0002A,9,8, 2) RX_MUX to TxFIFO
Modify_SPI_Reg(sdr, 0x0002A,5,4, 2) RX FIFO write clock to FCLK1

I would like to understand which approach is the right, one of the two that I presented or other that I do not know.
Also, there is a on board Loopback, outside of the LMS7002. Would this specific hardware be more suitable for my case. If so, how can i activate this hardware.

If someone could help me, I would be grateful.
Thank you.

ricardas · 22 May 2025 05:54

Just to clarify, you want to transmit and at the same time receive the same signal over RF loopback?

that’s for digital loopback, Rx would output the same data that was fed into Tx.

LimeSDR USB on board loopback can be controlled with FPGA register 0x0017

github.com/myriadrf/LimeSuite

src/boards_wxgui/pnlLimeSDR.cpp

master


      
          void pnlLimeSDR::OnGPIOChange(wxCommandEvent& event)
          {
              uint16_t addr = 0x0017;
              uint16_t value = 0;
              value |= chkRFLB_A_EN->GetValue() << 0;
              value |= chkTX1_2_LB_AT->GetValue() << 1;
              value |= chkTX1_2_LB_SH->GetValue() << 2;
          
              value |= chkRFLB_B_EN->GetValue() << 4;
              value |= chkTX2_2_LB_AT->GetValue() << 5;
              value |= chkTX2_2_LB_SH->GetValue() << 6;
          
              if(lmsControl && LMS_WriteFPGAReg(lmsControl, addr, value))
              lime::error("Board loopback cahnge failed");
          }

Petren · 28 May 2025 21:29

I want to periodically receive some samples of my transmission.

I was trying to write the register 0x0017 with the writeRegister function of the SoapySDR on Python. However, apparently, it does no work. When I try to read that register, no change has been done.
Exemple of my code:

def Modify_SPI_Reg(sdr, addr , msb, lsb, value):
spiDataReg = sdr.readRegister(“RFIC0”, addr)
spiMask = (~(~0 << (msb - lsb + 1))) << (lsb)
spiDataReg = (spiDataReg & (~spiMask)) | ((value << lsb) & spiMask)
return sdr.writeRegister(“RFIC0”, addr, spiDataReg)

def LoopBack(sdr):

print(sdr.readRegister("RFIC0", 0x0017))

Modify_SPI_Reg(sdr, 0x17, 0 , 0 , 1)
Modify_SPI_Reg(sdr, 0x17, 1 , 1 , 1)
Modify_SPI_Reg(sdr, 0x17, 2 , 2 , 0)

print(sdr.readRegister("RFIC0", 0x0017))