I’m trying to add some custom logic into my LimeSDR-USB and need to access a register.
Reading through the RTL I’ve seen that register 24 is spare, and I have successfully used LMS_ReadFPGAReg and LMS_WriteFPGAReg to verify R/W operation here.
My question, is there a register map in documentation where this is laid out ?
Is there a more general access method for accessing any register (in LMS7002M, FPGA, FX3 etc).
Is there any support for self clearing registers ? What about clock domains for the registers ?
@Zack I have added a 1PPS into GPIO header, and I can read the register and see the pulse at times when lucky enough to poll it.
I’m wanting to add a hex string into the stream when 1PPS fires with a register based trigger, where would you suggest is the best place to insert such functionality into the FPGA ? I’m VHDL fluent
A bit hacky:
You could hitchhike the PPS info into the packet header.
The first two documented bits (see packet structure, bits 3 and 4) are basically only TX relevant, and therefore unused for RX packets.
The downside is that thus is only streamed back at payload granularity. But with a PPS, there is plenty of room to serialize quite some information on the relative timing of pps wrt to sample count.
