LimeSDR RF loopback testing


I am new to LimeSDR platform. I am trying to enable 802.15.4e TSCH protocol using GNU Radio with LimeSDR-USB A. Because the protocol is time slotted protocol I have strict timing constraints. I am trying to do a round trip delay analysis of the test setup using RF loopback enabled on the FPGA. I have noticed the following thing (correct me if I am wrong):

  • The IQ data stream I am sending never comes back as it is, the received stream has reduced amplitude and also the digital sample values are changed. Because I am not using the LMS7002M chip shouldn’t the RF loopback enable me to receive the same data stream?
    Also, I tried using the to measure the delay but it fails because the argMax index and corrIndex are not converging. I have enabled the loopback by writing 0x55 to the FPGA register 0x0017 ( I took the values from the Limesuite Implementation) but the results are still not converging.

Any help would be highly appreciated.


Tagging @Zack.

Could you be more specific on this? Not sure if I understand your setup correctly.

Anyway, RF loopback test means, that you have this chain:

PC --> FPGA --> LMS7002M Tx (ADC, …, RF) --> LMS7002M Rx (RF, …, DAC) -> FPGA -> PC

As you can see, RF is included in the chain. Hence no wonder that your signal gain will be different and received samples doesn’t match with those were sent.

I am trying to do this setup

Message Source -> GNU Radio -> FPGA TX----> FPGA RX -> GNU Radio -> Message Sink.
The gnu radio is running 802.15.4 MAC and PHY layers. So when I send the message I measure the system time lets say t1 and when I receive my message I get the time t2. So I measure the overall round-trip latency as t2-t1.
Next, I want to measure the timing from USBMon logs, that’s why I was curious to what the " RF loopback CH A" and " RF loopback CH B" as found in Board Controls of Limesuite actually means as it would help me figure out a method to identify the packets correctly when I receive them with USBmon.

Also is there any way to disable the LMS7002M chip and loop the stream back from the FPGA?

The simplest way would be to use loopback at the LMS7002M digital interface. It is easy to do using LimeSuiteGUI:

  1. Set RX_MUX to TxFIFO (0x002A[11:10] = 1)
  2. Set RX FIFO write clock to FCLK1 (0x002A[1:0] = 0)

Thanks a lot for the help. I will try it out. Just to clarify these addresses are LMS7002M registers and using these settings I won’t need to set the 0x0017 address using the Board SPI, right?


Thank you!