LimeSdr-pcie FPGA utilization

I could not find a FPGA utilization report for the Quartus project. I wonder how much space is left for custom FPGA code as the device is smaller than the USB boards have. Has anybody compiled the full code.

I was hoping to give you an answer by building it, but there seem to be a missing piece of IP in the PCIe design (00e31b95):

Warning (12019): Can't analyze file -- file limesdr-pcie_xillybus_core/xillybus.v is missing

However, the USB version builds fine (b4dbef59) at 63% utilization:

; Device                             ; EP4CE40F23C8                                ;
; Timing Models                      ; Final                                       ;
; Total logic elements               ; 24,897 / 39,600 ( 63 % )                    ;
;     Total combinational functions  ; 21,137 / 39,600 ( 53 % )                    ;
;     Dedicated logic registers      ; 15,051 / 39,600 ( 38 % )                    ;

There is a document with details of the PCIe core, which needs to be downloaded separately:

Does it violate the Xillybus license to include the generated files?

At first I was thinking that the EP4CE40 included a PCIe HIP, but I realised it does not, hence the Xillibus soft core.

You have to get that core yourself due to the licence. It’s not open source, sadly.

The Xillybus seem to be built on top of the HIP, and not a soft IP as I suspected previously.

I would assume it provides a FIFO interface which is similar to the GPIF II on the Cypress FX3 as well as out of the box the Xilly OS drivers.

However, the Altera modular Scatter-Gather DMA IP could also be an option, but that might require some work on the driver/software side.

Contributions of a completely free and open source replacement, or failing which at least IP that is bundled with the tools, would be very welcome!