Using limesuite 18.04.0-PothosSDR-2018.04.08-vc14-x64 (using debug log mode), i tried opening the config file previously posted above and got these errors:
[15:55:50] DEBUG: Estimated reference clock 30.6587 MHz
[15:55:50] INFO: Reference clock 30.72 MHz
[15:55:50] INFO: Connected Control port: LimeSDR-USB FW:4 HW:4 Protocol:1 GW:2.16 Ref Clk: 30.72 MHz
[15:56:14] DEBUG: INT 92, FRAC 786432, DIV_OUTCH_CGEN 2
[15:56:14] DEBUG: VCO 2880.00 MHz, RefClk 30.72 MHz
[15:56:14] DEBUG: csw 247; interval [244, 251]
[15:56:14] ERROR: TuneVCO(CGEN) - failed to lock (cmphl!=3)
[15:56:14] ERROR: SetFrequencyCGEN(480 MHz) failed
[15:56:14] DEBUG: M=240, N=24, Fvco=1200.000 MHz
[15:56:15] ERROR: SetPllFrequency: error configuring phase
[15:56:15] DEBUG: M=240, N=24, Fvco=1200.000 MHz
[15:56:15] DEBUG: M=172, N=2, Fvco=1290.000 MHz
[15:56:15] ERROR: SetPllFrequency: error configuring phase
[15:56:15] DEBUG: M=172, N=2, Fvco=1290.000 MHz
[15:56:31] DEBUG: INT 92, FRAC 786432, DIV_OUTCH_CGEN 2
[15:56:31] DEBUG: VCO 2880.00 MHz, RefClk 30.72 MHz
[15:56:31] DEBUG: csw 245; interval [242, 249]
[15:56:31] DEBUG: M=240, N=24, Fvco=1200.000 MHz
[15:56:31] ERROR: SetPllFrequency: error configuring phase
[15:56:31] DEBUG: M=240, N=24, Fvco=1200.000 MHz
[15:56:31] DEBUG: M=172, N=2, Fvco=1290.000 MHz
[15:56:31] ERROR: SetPllFrequency: error configuring phase
[15:56:31] DEBUG: M=172, N=2, Fvco=1290.000 MHz
[15:56:31] INFO: CGEN frequency set to 480.000000 MHz