Hello,
I’ve been looking through the LimeSDR-Mini-v2_GW gateware repo in attempts to make some modifications to the rxtx data flows, and I ran into issues while trying to make use of the included test benches.
It appears that the included test benches are out of date, or at least they don’t match up with the entities they use. Are there any future plans to update these to make them usable? I tried to fix them as best as I could but I seem to be running into an issue when data goes into the “fifodc_w32x1024_r128” where it is producing no output data in the simulator. It seems this entity is under a ‘.sbx’ file rather than an associated “.vdhl” so it’s hard to investigate.
For context I’m using Lattice Diamond 3.13.0.56.2 with ModelSim for Simulation, setup as instructed through the documentation.
Any help with this would be greatly appreciated,
Thanks!
Hi @Calicus,
you are right, test benches are out of date since GW was ported from LimeSDR Mini V1 (Altera FPGA) to LimeSDR MINI V2 (Lattice FPGA).
Most likely issue that you are seeing is caused because testbech is using fifodc_w32x1024_r128 files which are meant to be used in actual synthesis, place and route. If I remember correctly there should be an option to generate simulation model in Lattice Diamond IP wizard.
regards,
Vytautas
Thank you for pointing me in the right direction, the IPExpress helped me with the fifodc!
Another question though, is there a document on the packet and header formats? Trying to adjust the testbench has been somewhat difficult as I cannot locate the exact structure in tandem with the samples given here.
Thanks!
Actually if you would be able to point me in any other documentation (preferably more recent than LimeSDR-Mini_Gateware_Description_V01r00.pdf or StreamProtocol.pdf ) on the Gateware of the LimeSDR mini 2.0 FPGA, that would be greatly appreciated.
