LimeSDR Loopback Test Failures/Tune Failures

I have seen a fair amount of posts about the loopback test failures but I have yet to see any “resolution” to the issues.
I am currently running with a LimeSDR with the following firmware using limesuite v20.10.0

$./LimeUtil --update
Connected to [LimeSDR-USB [USB 3.0] 9072C00D5071E]
Existing firmware is same as update (4)
Existing gateware is same as update (2.23)

Running the LimeQuickTest:

[ RF Loopback Test ]
Note: The test should be run without anything connected to RF ports
->Configure LMS
->Run Tests (TX_2-> LNA_L):
  CH0 (SXR=800.0MHz, SXT=805.0MHz): Result:(-15.8 dBFS, 5.00 MHz) - PASSED
  CH1 (SXR=800.0MHz, SXT=805.0MHz): Result:(-17.4 dBFS, 5.00 MHz) - PASSED
->Run Tests (TX_1 -> LNA_W):
  CH0 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-27.9 dBFS, 5.00 MHz) - FAILED
  CH1 (SXR=1800.0MHz, SXT=1805.0MHz): Result:(-28.9 dBFS, 5.00 MHz) - FAILED
->Run Tests (TX_2-> LNA_H):
  CH0 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-17.1 dBFS, 5.00 MHz) - PASSED
  CH1 (SXR=2500.0MHz, SXT=2505.0MHz): Result:(-15.3 dBFS, 5.00 MHz) - PASSED
->RF Loopback Test FAILED

I have not been able to determine why these fail.
I often run into issues with tuning:
Where if I setup logging to debug using the LimeSuiteGUI I see lots of “tune fails”

[17:35:14] INFO: Disconnected control port
[17:35:19] INFO: Reference clock 30.72 MHz
[17:35:19] INFO: Connected Control port: LimeSDR-USB FW:4 HW:4 Protocol:1 GW:2.23 Ref Clk: 30.72 MHz
[17:35:33] INFO: SXT frequency set to 1200.000000 MHz
[17:35:39] DEBUG: INT 152, FRAC 262144, DIV_LOCH 1, EN_DIV2_DIVPROG 0
[17:35:39] DEBUG: VCO 4800.00 MHz, RefClk 30.72 MHz
[17:35:39] DEBUG: ICT_VCO: 192
[17:35:39] DEBUG: csw=64 cmphl=0
[17:35:39] DEBUG: csw=96 cmphl=0
[17:35:39] DEBUG: csw=112 cmphl=0
[17:35:39] DEBUG: csw=120 cmphl=0
[17:35:39] DEBUG: csw=124 cmphl=0
[17:35:39] DEBUG: csw=126 cmphl=0
[17:35:39] DEBUG: csw=127 cmphl=0
[17:35:39] DEBUG: Failed to lock
[17:35:39] DEBUG: csw=192 cmphl=0
[17:35:39] DEBUG: csw=224 cmphl=3
[17:35:39] DEBUG: csw=208 cmphl=3
[17:35:39] DEBUG: csw=200 cmphl=3
[17:35:39] DEBUG: csw=196 cmphl=2
[17:35:39] DEBUG: csw=198 cmphl=2
[17:35:39] DEBUG: csw=199 cmphl=2
[17:35:39] DEBUG: CSW: lowest=193, highest=199, selected=196
[17:35:39] DEBUG: cmphl=2
[17:35:39] DEBUG: VCOL : csw=196 tune ok
[17:35:39] DEBUG: ICT_VCO: 192
[17:35:39] DEBUG: TuneVCO(SXT) - VCO too high
[17:35:39] DEBUG: VCOM : csw=0 tune fail
[17:35:39] DEBUG: ICT_VCO: 192
[17:35:39] DEBUG: TuneVCO(SXT) - VCO too high
[17:35:39] DEBUG: VCOH : csw=0 tune fail
[17:35:39] DEBUG: Selected: VCOL
[17:35:39] INFO: SXT frequency set to 1200.000000 MHz

Here is a link to the register settings that I am running currently.

If anyone has some ideas that would be super helpful.