Is the block diagram right or wrong?

Hello all,
I found in the CDS Control Diagram , the MCLK2 clock on the pad is connected with mclk1 port of LML Module, While the MCLK1 clock on the pad is connected with mclk2 port of LML Module, Are these connection right or wrong? According to the common sense, MCLK1 should conect mclk1, While MCLK2 should conect mclk2. Could you pls help me to check it and give me response? thanks very much!

@ Ricardas Jonaitis

Any updates on this?

Someone has said that the FPGA code has FCLK1 derived from MCLK2, that would be consistent with this diagram.
But the newest FPGA code for Mini v2 has FCLK1 derived from MCLK1.

So what configuration is correct? Is mclk1 internal signal connected to PAD MCLK2 as per this diagram?