I’d like to modify the LimeSDR-USB’s gateware by putting an interpolation filter along its transmit path. I’ve used Matlab to generate an interpolation filter, so that’s prepared, and I just need to figure out how to interface it with what’s already in the gateware design. I’ve taken a good look through the gateware in Quartus both in the VHD files and through the RTL Viewer and my guess would be that the easiest place to put it would be after the txiqmux block in the rxtx_top block, as seen from the gateware description document. I need a bit of help understanding exactly how the gateware works, however.
For starters, I noticed the bits leaving the txiqmux leave as 13 bit high and low lines, which become a 12 bit IQ line with a select before going to the LMS IC. According to the Stream Protocol document (https://wiki.myriadrf.org/Stream_Protocol), the 12 bit compressed samples represent a 12-bit (x2) IQ sample pair every three byte indices or basically every three times the TX_DIQ line updates. Am I getting that right? So if that is the case, in order to run the samples through the filter, I’d additionally need code to return it to a “standard” form, and then more code to convert the output of the filter back into this form.
Secondly, how should I handle the update in rate after the interpolation filter? My guess would just be to set the sample rate to the final target rate in the GNURadio design I’m testing with, but again, I’m not really sure.
Odds are I’m going about this in a silly way and there’s probably a better way to insert a filter into the FPGA. If anyone here can help me understand how to best go about this and what I should consider while doing so, I’d greatly appreciate it.