How to write GNU radio source in FPGA EEPROM?


Hi. I’m new Lime SDR mini user. I am trying to write my FM receiver program made by GNU radio in FPGA EEPROM.
How can i write my program in FPGA EEPROM?


What I think you are asking is not really done, unless you are designing a standalone product to sell.

There is no simple tool to do what you are asking. I think what you are asking for is complex requiring many years of knowledge in at least two diverse technical areas. GNU Radio companion is fantastic at hiding the underlying complexity and is running on a machine with near infinite resources (gigabytes of RAM, CPU’s running at multiple GHz) in many ways by comparison with a typical FPGA (a few kilobytes of distributed RAM, no CPU, but typically clocked at maybe 100 MHz). What you are basically asking is how to squeeze an elephant into a match box, this normally involves redesigning the elephant to be much much much much much smaller.

One path would be to invest many months/years learning basic and advanced DSP (Digital Signal Processing) techniques (and the associated tips and tricks to reduce the processing resources required).
In addition also invest many months/years learning how to program FPGA’s, and programming is not really the right word, it is more like designing digital circuits that everything happens nearly at once in parallel. Or you might be able to license some blocks from FPGA vendors that may or may not do what you want.

I’d probably start by learning the DSP first.

If I was trying to learn to program FPGA’s I would start by buying a FPGA development board (that did not cost very much for when you/I eventually screw up and break it), and learn how to blink a LED. That is the “Hello world!” equivalent with typical hardware design. Then once I was happy that the toolchain was working and that I could program the device I’d learn how to implement a FIR filter (Finite impulse response) maybe 4-bits wide with 3 taps depending on the resources in the chip. And then I would build up my repertoire from there. But be aware that the typical design, test and implementation phases with FPGA’s can be up to ten times longer than working with general purpose CPU’s.