It seems that changing the bandwidth impacts the received samples and their timestamps.
I noticed this when receiving the same signals on 2 Limes to be able to compare their timestamps:
- if I never change the bandwidth, then the timestamp difference of the 2 Limes stays the same
- if I change the bandwidth of one Lime, then the timestamp difference changes.
It seems that depending on the values of the bandwidth change, I may end up seeing a signal at an early timestamp (as if samples were lost and the RX counter not incremented enough) or at a late timestamp (as if new samples were added and/or the RX counter incremented too many times).
@zack Can someone with knowledge in the FPGA confirms? Is this something that can be fixed?
Note that I don’t care about the samples received during the bandwidth change, but I would like to be able to change the bandwidth without having to resynchronize the 2 Limes.