I assume that the Lattice FPGA is acting as a FIFO controller for the FTDI FT601 USB3 device. How much of the FPGA is being utilized for this function?
The FPGA is being used for all sorts of other stuff, including sample timestamping and implementing a soft-core processor. You can get the RTL source here:
There is also detailed documentation in the same repo.
Hello Andrew, I think the FPGA doc is for Altera, Is there a doc or a block diagram for Lattice for mini v2?
Hmm, looking at:
It says updated for Mini v2 and mentions Lattice Diamond, but then talks about Altera and NIOS-II.
@VytautasB has this document not been fully updated?
Hi @notorious2024, @andrewback,
looks like 3.1 section is outdated, somehow I managed to push older version of the document. Other sections are up-to date according to V2 GW.
I will update 3.1 section. Anyway there is not much difference between v1 and v2 in terms of structure. NIOSII CPU is replaced with Mico32 and some minor changes in clock network which is described in 3.2 section.
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