FPGA Resource Utilization as FIFO Controller

I assume that the Lattice FPGA is acting as a FIFO controller for the FTDI FT601 USB3 device. How much of the FPGA is being utilized for this function?

The FPGA is being used for all sorts of other stuff, including sample timestamping and implementing a soft-core processor. You can get the RTL source here:

There is also detailed documentation in the same repo.