"ERROR: MCU FIFO full" on LimeSDR Mini

Projects LimeSDR
1

I recently received my LimeSDR Mini and have so far been unable to get it to work. After connecting to it in LimeSuiteGUI, I get some sort of error whenever I try to do something. For example, when I hit the “Calibrate RX” button, I get “ERROR: MCU FIFO full”. When I hit “Chip–>GUI” and then “GUI–>Chip”, I get “ERROR: SetFrequencyCGEN(484.004 MHz) failed” followed by “ERROR: SetPllFrequency: timeout, busy bit is still 1”.

I’m running Ubuntu 16.04 with the development version of LimeSuite (but had the same issues on the latest released version).

Does anyone have any idea what’s going on here?
Thanks in advance!

2

Same problem here. MCU FIFO FULL and several other MCU errors.

Unable to compile last Soapy with Lime support.

Ubuntu 16.04 also.

No problem in SDRConsole v3 in Windows.

3

Same problem here, on OSX. I have tried recompiling LimeSuite, and when I did this, I was then able to get the Limesdr mini working with gqrx.
However, I cannot run through the LimeSDR-usb quicktest. LimeUtil --info reports

Version information:
Library version: v18.03.0-unknown
Build timestamp: 2018-03-25
Interface version: v2017.12.0
Binary interface: 18.03-1

System resources: …

Supported connections:

  • FT601
  • FX3
  • PCIEXillybus

Can anyone report that they have worked through the LimeSDR-USB quick test page using the LimeSDR-mini? I get the following DEBUG information:

[22:39:18] INFO: Disconnected control port
[22:39:26] INFO: Reference clock 40.00 MHz
[22:39:26] INFO: Connected Control port: LimeSDR-Mini FW:5 HW:0 Protocol:1 GW:1.24 Ref Clk: 40.00 MHz
[22:41:22] DEBUG: INT 66, FRAC 786432, DIV_OUTCH_CGEN 3
[22:41:22] DEBUG: VCO 2081.28 MHz, RefClk 30.72 MHz
[22:41:22] DEBUG: ICT_VCO_CGEN: 31
[22:41:22] DEBUG: TuneVCO(CGEN) - VCO too low
[22:41:22] ERROR: SetFrequencyCGEN(260.16 MHz) failed
[22:41:22] DEBUG: M=234, N=6, Fvco=1268.280 MHz
[22:41:22] ERROR: SetPllFrequency: timeout, busy bit is still 1
[22:41:22] DEBUG: M=252, N=7, Fvco=1170.720 MHz

I also have the other LimeSDR, which gets through all tests perfectly, and gives none of these messages.
Cheers Hugh

4
5

Hi,
OK - I plug in my new LimeSuite Mini, and I am able to do a LimeUtil --update:

Hughs-MacBook:~ hugh$ LimeUtil --update
Connected to [LimeSDR Mini [USB 3.0] 1D3AC988444E8A]
[100%] 303104/303104 Bytes programming: completed (/Users/hugh/.local/share/LimeSuite/images/18.03/LimeSDR-Mini_HW_1.1_r1.24.rpd)
Programming update complete!
Hughs-MacBook:~ hugh$

I then run LimeSuiteGUI, turn on LogLevel:debug, and connect the USB-3.0 device. At this stage, the LDO settings are all clear. If I press the Default button, it shows this:

08:56:00] INFO: Disconnected control port
[08:56:11] DEBUG: Claimed Interface
[08:56:11] DEBUG: Estimated reference clock 40.0014 MHz
[08:56:11] INFO: Reference clock 40.00 MHz
[08:56:11] INFO: Connected Control port: LimeSDR-Mini FW:5 HW:0 Protocol:1 GW:1.24 Ref Clk: 40.00 MHz
[08:56:15] DEBUG: INT 121, FRAC 0, DIV_LOCH 1, EN_DIV2_DIVPROG 0
[08:56:15] DEBUG: VCO 5000.00 MHz, RefClk 40.00 MHz
[08:56:15] DEBUG: ICT_VCO: 180
[08:56:15] DEBUG: csw=64 cmphl=0
[08:56:15] DEBUG: csw=96 cmphl=0
[08:56:15] DEBUG: csw=112 cmphl=0
[08:56:15] DEBUG: csw=120 cmphl=0
[08:56:15] DEBUG: csw=124 cmphl=0
[08:56:15] DEBUG: csw=126 cmphl=0
[08:56:15] DEBUG: csw=127 cmphl=0
[08:56:15] DEBUG: Failed to lock
[08:56:15] DEBUG: csw=192 cmphl=0
[08:56:15] DEBUG: csw=224 cmphl=3
[08:56:15] DEBUG: csw=208 cmphl=0
[08:56:15] DEBUG: csw=216 cmphl=2
[08:56:15] DEBUG: csw=220 cmphl=2
[08:56:15] DEBUG: csw=222 cmphl=2
[08:56:15] DEBUG: csw=223 cmphl=3
[08:56:15] DEBUG: Failed to lock
[08:56:15] DEBUG: cmphl=2
[08:56:15] DEBUG: VCOL : csw=219 tune ok
[08:56:15] DEBUG: ICT_VCO: 180
[08:56:15] DEBUG: TuneVCO(SXT) - VCO too high
[08:56:15] DEBUG: VCOM : csw=0 tune fail
[08:56:15] DEBUG: ICT_VCO: 180
[08:56:15] DEBUG: TuneVCO(SXT) - VCO too high
[08:56:15] DEBUG: VCOH : csw=0 tune fail
[08:56:15] DEBUG: Selected: VCOL
[08:56:15] DEBUG: INT 116, FRAC 0, DIV_LOCH 1, EN_DIV2_DIVPROG 0
[08:56:15] DEBUG: VCO 4800.00 MHz, RefClk 40.00 MHz
[08:56:15] DEBUG: ICT_VCO: 180
[08:56:15] DEBUG: csw=64 cmphl=0
[08:56:15] DEBUG: csw=96 cmphl=0
[08:56:15] DEBUG: csw=112 cmphl=0
[08:56:15] DEBUG: csw=120 cmphl=0
[08:56:15] DEBUG: csw=124 cmphl=0
[08:56:15] DEBUG: csw=126 cmphl=0
[08:56:15] DEBUG: csw=127 cmphl=0
[08:56:15] DEBUG: Failed to lock
[08:56:15] DEBUG: csw=192 cmphl=2
[08:56:15] DEBUG: csw=224 cmphl=3
[08:56:15] DEBUG: csw=208 cmphl=3
[08:56:15] DEBUG: csw=200 cmphl=3
[08:56:15] DEBUG: csw=196 cmphl=2
[08:56:15] DEBUG: csw=198 cmphl=3
[08:56:15] DEBUG: csw=197 cmphl=2
[08:56:15] DEBUG: CSW: lowest=189, highest=197, selected=193
[08:56:15] DEBUG: cmphl=2
[08:56:15] DEBUG: VCOL : csw=193 tune ok
[08:56:15] DEBUG: ICT_VCO: 180
[08:56:15] DEBUG: TuneVCO(SXR) - VCO too high
[08:56:15] DEBUG: VCOM : csw=0 tune fail
[08:56:15] DEBUG: ICT_VCO: 180
[08:56:15] DEBUG: TuneVCO(SXR) - VCO too high
[08:56:15] DEBUG: VCOH : csw=0 tune fail
[08:56:15] DEBUG: Selected: VCOL
[08:56:15] DEBUG: INT 57, FRAC 385875, DIV_OUTCH_CGEN 18
[08:56:15] DEBUG: VCO 2334.72 MHz, RefClk 40.00 MHz
[08:56:15] DEBUG: ICT_VCO_CGEN: 31
[08:56:15] DEBUG: csw=64 cmphl=0
[08:56:15] DEBUG: csw=96 cmphl=0
[08:56:15] DEBUG: csw=112 cmphl=0
[08:56:15] DEBUG: csw=120 cmphl=0
[08:56:15] DEBUG: csw=124 cmphl=0
[08:56:15] DEBUG: csw=126 cmphl=0
[08:56:15] DEBUG: csw=127 cmphl=0
[08:56:15] DEBUG: Failed to lock
[08:56:15] DEBUG: csw=192 cmphl=3
[08:56:15] DEBUG: csw=160 cmphl=3
[08:56:15] DEBUG: csw=144 cmphl=0
[08:56:15] DEBUG: csw=152 cmphl=2
[08:56:15] DEBUG: csw=156 cmphl=2
[08:56:15] DEBUG: csw=158 cmphl=3
[08:56:15] DEBUG: csw=157 cmphl=2
[08:56:15] DEBUG: CSW: lowest=151, highest=157, selected=154
[08:56:15] DEBUG: cmphl=2
[08:56:15] DEBUG: M=160, N=4, Fvco=614.400 MHz
[08:56:15] DEBUG: M=160, N=4, Fvco=614.400 MHz

THe LDO screen now has about half of the items checked. The “Power controls” section has everything ticked except for PD_LDO_DIGIp1, PD_LDO_DIGIp2 and PD_LDO_SPIBUF. There is nothing ticked in the “Short Noise Filter Resistor” section.
Then, I switch to the SXT tab, and press “Calculate”, and I get this:

[08:58:03] DEBUG: INT 0, FRAC 0, DIV_LOCH 0, EN_DIV2_DIVPROG 0
[08:58:03] DEBUG: VCO 4280.00 MHz, RefClk 0.00 MHz
[08:58:03] DEBUG: ICT_VCO: 180
[08:58:03] DEBUG: TuneVCO(SXR) - VCO too low
[08:58:03] DEBUG: VCOL : csw=0 tune fail
[08:58:03] DEBUG: ICT_VCO: 180
[08:58:03] DEBUG: TuneVCO(SXR) - VCO too low
[08:58:03] DEBUG: VCOM : csw=0 tune fail
[08:58:03] DEBUG: ICT_VCO: 180
[08:58:03] DEBUG: TuneVCO(SXR) - VCO too low
[08:58:03] DEBUG: VCOH : csw=0 tune fail
[08:58:03] DEBUG: Selected: VCOH
[08:58:03] ERROR: SetFrequencySXR(2140 MHz) - cannot deliver frequency

… Does any of this help?

Cheers Hugh

6

Some success now. OK - If I do this:

  1. Connect SDR
  2. Select SXR or SXT tab, and THEN press “Default”

Then the Calibrate and Tune appear to work. There is something strange happening with this process - If I do:

  1. Connect SDR
  2. Select CLKGEN, and THEN press “Default”

I get a greyed out CLK_L of 121000976.562 MHz. So - I press “Default” again (i.e. twice now), and it changes to 15.360MHz, and the Calculate and Tune now works.
I notice that this is happening with my LimeSDR units, and also the LimeSDR-Mini units.
I still cannot get through the initial test/setup process though.
CHeers Hugh

7

I get most success in Ubuntu 16.04 by using pybombs version. Totally unable to make it work using git source nor deb packages. Keep trying thoug.