I have been trying to modify the LimeSDR-mini gateware but multiple attempts to do so have failed with unexpected outcomes and no idea why it happened.
I started out by trying to build the LimesdrMini-lms7_trx gateware design. I built a simple blinky module and tried to connect it to the onboard led.
Here’s a listing of the modifications :
listing #1.added the code below to lms7_trx_top.vhd (the code below is the module instantiation, its definition is in listing 3.) ``` architecture arch of lms7_trx_top is --declare signals, components here COMPONENT blinky PORT ( clk : IN STD_LOGIC; led_R : OUT STD_LOGIC; led_G : OUT STD_LOGIC ); END COMPONENT; ``` ---
listing #2.also lms7_trx_top.vhd (changes made in the last 2 lines here):
inst4_general_periph_top : entity work.general_periph_top generic map( DEV_FAMILY => DEV_FAMILY, N_GPIO => C_INST4_GPIO_N ) port map( -- General ports clk => FT_CLK, reset_n => reset_n_ft_clk, -- configuration memory to_periphcfg => inst0_to_periphcfg, from_periphcfg => inst0_from_periphcfg, -- Dual colour LEDs -- LED1 (Clock and PLL lock status) led1_pll1_locked => inst1_pll_locked, led1_pll2_locked => inst1_pll_locked, led1_ctrl => inst0_from_fpgacfg.FPGA_LED1_CTRL, -- changes : led1_g => open, -- changed from FPGA_LED_G to open led1_r => open, -- changed from FPGA_LED_R to open
listing #3.Added a new verilog file (I work in verilog) :
module blinky( input wire clk, output wire led_g, output wire led_r ); reg[29:0] counter; always @(posedge clk) begin counter[29:0] <= counter[29:0]+1'b1; end assign led_r = counter; assign led_g = counter; endmodule
However I was not able to get the design to work. I faced many issues :
Issue #1 :The design itself did not compile out of the box :
Error (12006): Node instance “lms_ctr_inst0” instantiates undefined entity “lms_ctr”. Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP.
Attempted Solution :Launched the ip upgrade tool and performed automatic upgrade. Even here, the lms_ctr entity failed as shown below but this issue did not come up again. ![image|690x178](upload://fR0gvDb8hrVFrnFS8IqzLtMNYoJ.jpeg)
Issue #2 :After the first solution, recompilation brought up the following errors: ![image|690x91](upload://kOt0KWJGHP9l1mTkU2FYoMHhRKD.png)
The above seems to be a declaration error.
Attempted solution :I removed/commented out all the lines mentioned in the error statements. The compilation proceeded.
I then went further to execute the modifications in order to run the blinky program.
I then went ahead and built it by loading the config file and replacing the default lms7 page with my newly built version :
and then uploaded the new LimeSDR-Mini_lms7_trx_HW_1.2_auto.rpd file to the limeSDR mini using the LimeSuite.
However I saw no change in blinking. I tried to change the blinking rate by changing values in listing #3 but there was still no change.
Q1. What is the issue here?
Q2. Is there any debugger that I can hook up with the fpga inside to examine and better understand the process? Which debugger is supported by max10? (I tried to look at altera’s sites for answers, but there was no straight forward one)