Communication interfaces between Raspberry-PI and FPGA

#1

Hello all,

The LimeNET-Micro hardware description describes I2C, SPI and UART interfaces in part 3.8. I’d like to understand all of this a bit better and started looking into the Gateware toplevel and pin constraints.

Is there a specification somewhere what the interfaces are used for, and what commands are available?
Are there any debugging/test tools available?

Up to now, I guessed that RAPI_SPI0 is not used, RAPI_SPI1 is connected to the Nios II (through an Avalon FIFO), that there are commands that are parsed in LimeNET-Micro_lms7_trx/software/lms_ctr_app/main.c, and that I2C is not used to communicate between Raspberry Pi and Nios II. I hope that is correct so far, and would appreciate a short confirmation or correction.

#2

Hi @mpb,

There are a lot of possibilities. Let me describe what is implemented right now without digging into every possibility separately.

  1. I2C interface. Currently FPGA is a master of I2C bus. Currently communication with all the devices on this bus is initiated from FPGA. There is no communication between FPGA and RPi via I2C at all.
  2. FPGA_SPI interface. All the devices on this bus (check Table 14 from the link provided by you) are accessed from FPGA.
  3. RAPI_SPI0 & RAPI_SPI1. These interfaces currently are not used. They are reserved for LMS7002M control and IQ data if USB interface is not assembled.
#3

Hi @Zack

so I wasn’t all wrong :slight_smile:

If RAPI_SPI0 is not used for control, then how do control commands get from RPi to FPGA? Through the same USB FIFO as the IQ data?

If you wanted to retrieve the TCXO and GPS lock status (which are indicated by LED4 and LED5) from an application running on the RPi, what path would you use?