We are building a multi channel system and are looking for suggestions on the system level clock architecture.
The plan is as follows:
- Receive DIQ data (RF2BB) from multiple chips using a single MCLK (received from any one of the LMS chips). This single MCLK will be routed inside the FPGA using a global clock network.
- Generate FCLK for BB2RF from a PLL (inside the FPGA) using the same MCLK used for RF2BB. The generate PLL generated FCLK will again be routed through out the FPGA using a global clock network.
The objective is to synchronize all the LMS chips on both Tx and Rx.