If the question is, can you do this automatically, trivially or even just generally, the answer is likely, no.
If the questions is, can you study the operation of a GNU Radio flow graph that does something in particular and that is suited to being implemented in the FPGA, then rewrite this in Verilog, the answer is, possibly.
I’m afraid the question is far too vague. If you have a flowgraph that, for example, transmits a tone, receives and retransmits frames in a simple manner, or turns an indicator on when it detects a signal, this seems achievable. But if you want to run a complex stack with a wideband air interface, without any host, this seems unlikely.