AGC and dc offset


1) We need to use the LMS7002M in the AGC mode and are using the LimeSuite API.
When we turn ON the AGC, the dc offset in the I and Q channels changes with the input signal level.
2) Please advise if this is expected. If yes, how to do we fix this as the rest of our chain does not expect any dc in the I and Q lines.
3) What is the lower threshold of the RSSI detector used by the AGC and what is the dynamic range of the AGC. (The gain range of the LMS itself is 90dB so does the AGC also have a dynamic range of 90dB).
4) What is the input power range (to the chip) over which the dynamic range of the AGC can be observed.
Thank you for your time in answering our queries and helping us out,


@Zack ?


Hello @Zack,
I am quite confused now!
Earlier with certain gain values for the LNA , TIA and PGA our maximum input signal level till ADC saturation was about -45dBm.
With the AGC enabled the saturation level is at +10dBm.
When you say digital AGC may I ask if you mean a digitally controlled AGC but the gain control is of analog components?
If so, then I suppose my previous questions are still valid.
Thank you for your inputs,


OK, maybe I misunderstood something. Was assuming you are using digital AGC. Could you tel me how do you turn AGC on in your case.


Using the MCU api
lms -> MCU_AGCStart(wantedRSSI);


Hi @EnthuMan,

OK, you are using analog AGC, sorry for confusion. Removing my first post in order to not confuse others.

Provide this information, please:

  1. What is SXR frequency?
  2. What signal bandwidth?
  3. What test signal do you supply to RF Rx input (CW or modulated)?
  4. What is DC offset change, when you change input signal level?
  5. How do you measure DC offset change?

Hello @Zack,
What is SXR frequency? 2250
What signal bandwidth? 25MHz
What test signal do you supply to RF Rx input (CW or modulated)? CW
What is DC offset change, when you change input signal level? Did not measure it precisely but saw the signal shift along the y-axis when plotted the time domain data. Perhaps a few tens to ~200 either side of zero (12 bit ADC values)
How do you measure DC offset change? Otherwise we see it in a FFT plot.

Thanks for your help,


Hi @EnthuMan,

AGC dynamic range is LNA+PGA control (hence 60 dB). Minimum AGC threshold is approximately equal to DC level at ADC input. Absolute input power level range depends on frequency, since gain will vary accordingly. The AGC implemented in the MCU basically checks levels at ADC input, and acts accordingly. The input parameter “Crest factor” can be used to offset it (in CW case) or account for modulated signal PAPR differences. DC level changes are expected to some degree, since auto DC cancellation block uses fixed averaging windows (which can be controlled).