I’m trying to use the LimeSDR for a precisely timed receive only application. I need to know exactly the time of the sample.
I see there is a 64 bit RX timestamp … can this be accessed from LMS C api ?
Does the RX timestamp get generated on board power on and keep counting continuously through start and stop of the stream ? The timestamp comes from the LMS7002M I gather in the stream protocol. Can the LMS7002M RX timestamp be reset via register ?
Even if I get the FPGA to know the time I’m concerned about the variable latency when stream is started and stopped etc.
@andrewback any ideas ?