# XTRX max limelight frequency

**URL:** <https://discourse.myriadrf.org/t/xtrx-max-limelight-frequency/8613>\
**Category:** LimeSDR\
**Created:** [3 January 2025 21:04 UTC](https://discourse.myriadrf.org/t/xtrx-max-limelight-frequency/8613 "2025-01-03T21:04:01Z")\
**Posts on this page:** 5\
**Page:** 1

<div class="post-metadata">

**Author:** ![sdruser256](https://avatars.discourse-cdn.com/v4/letter/s/f14d63/32.png) [@sdruser256](https://discourse.myriadrf.org/u/sdruser256)\
**Post date:** [3 January 2025 21:04 UTC](https://discourse.myriadrf.org/t/xtrx-max-limelight-frequency/8613/1 "2025-01-03T21:04:01Z")

</div>

What is the max limelight interface frequency? I see there was some fine tuning of the Xilinx FPGA drive parameters to increase limelight interface max speed, what is the speed that was acheived?

> <https://github.com/myriadrf/LimeSDR-XTRX_GW/commit/cebbaeb9e60402ab3147093b552d1a88f06c2b82>

---

<div class="post-metadata">

**Author:** ![andrewback](https://avatars.discourse-cdn.com/v4/letter/a/22d042/32.png) [@andrewback](https://discourse.myriadrf.org/u/andrewback)\
**Post date:** [4 January 2025 10:14 UTC](https://discourse.myriadrf.org/t/xtrx-max-limelight-frequency/8613/2 "2025-01-04T10:14:50Z")

</div>

Tagging @VytautasB.

---

<div class="post-metadata">

**Author:** ![VytautasB](https://avatars.discourse-cdn.com/v4/letter/v/ccd318/32.png) [@VytautasB](https://discourse.myriadrf.org/u/VytautasB)\
**Post date:** [6 January 2025 11:21 UTC](https://discourse.myriadrf.org/t/xtrx-max-limelight-frequency/8613/3 "2025-01-06T11:21:28Z")

</div>

Hi @sdruser256,

Currently limelight is able to work with 122.88Mhz frequency on limelight interface. Take in mind that in order to work on such interface clock rate board requires cooling.

---

<div class="post-metadata">

**Author:** ![sdruser256](https://avatars.discourse-cdn.com/v4/letter/s/f14d63/32.png) [@sdruser256](https://discourse.myriadrf.org/u/sdruser256)\
**Post date:** [15 January 2025 17:37 UTC](https://discourse.myriadrf.org/t/xtrx-max-limelight-frequency/8613/4 "2025-01-15T17:37:06Z")

</div>

Thanks. How does this match with the “120 MSPS SISO / 90 MSPS MIMO” listed sample rate in the Specification section of [Lime Microsystems | LimeSDR XTRX](https://limemicro.com/sdr/limesdr-xtrx/)?

For 90 MSPS MIMO wouldn’t you need 90 \* 2 = 180 MHz limelight frequency?

---

<div class="post-metadata">

**Author:** ![VytautasB](https://avatars.discourse-cdn.com/v4/letter/v/ccd318/32.png) [@VytautasB](https://discourse.myriadrf.org/u/VytautasB)\
**Post date:** [16 January 2025 12:02 UTC](https://discourse.myriadrf.org/t/xtrx-max-limelight-frequency/8613/5 "2025-01-16T12:02:01Z")

</div>

In this case specs are from LMS7002 ADC/DAC sampling rate perspective not from limelight interface. You have to take into account interpolation/decimation settings in TSP blocks.

In SISO mode interpolation/decimation is bypassed so in order to transfer 120MSPS you will need 120MHz interface clock.

In MIMO mode interpolation/decimation=2 To transfer data from ADC/DAC running at 90MSPS limelight interface clock will be 90MHz.

Regards,  
Vytautas