# Wide Bandwidth Signal Acquisition with LimeSDR-PCIe?

**URL:** <https://discourse.myriadrf.org/t/wide-bandwidth-signal-acquisition-with-limesdr-pcie/522>\
**Category:** LimeSDR\
**Created:** [28 October 2016 20:47 UTC](https://discourse.myriadrf.org/t/wide-bandwidth-signal-acquisition-with-limesdr-pcie/522 "2016-10-28T20:47:32Z")\
**Posts on this page:** 1\
**Showing post:** 3

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**Author:** ![mzs](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/mzs/32/2678_2.png) [@mzs](https://discourse.myriadrf.org/u/mzs)\
**Post date:** [30 October 2016 08:45 UTC](https://discourse.myriadrf.org/t/wide-bandwidth-signal-acquisition-with-limesdr-pcie/522/3 "2016-10-30T08:45:36Z")

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My current understanding of the the LimeSDR USB and LimeSDR PCIe is that if one can do what you want then the other one probably can as well. But there might be a little bit more room in the FPGA on the USB over the PCIe for two reasons:

1. The [PCIe FPGA is smaller](https://discourse.myriadrf.org/t/altera-cyclone-fpga-30k-or-40k/396/2?u=mzs) EP4CGX **30** CF23C7N (PCIe) vs EP4CE **40** F23C8N (USB 3.0)
2. Additional [gateware needs to be loaded on the FPGA to drive the PCIe](https://discourse.myriadrf.org/t/max-bandwidth-of-dual-rx/307/9?u=mzs) so there would be less free room on the FPGA.

I have no idea about the latency, but I would guess that the PCIe latency would be lower.

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