# What is frame, sample source in position x and limelight interface settings?

**URL:** <https://discourse.myriadrf.org/t/what-is-frame-sample-source-in-position-x-and-limelight-interface-settings/4639>\
**Category:** System Development\
**Created:** [30 April 2019 06:21 UTC](https://discourse.myriadrf.org/t/what-is-frame-sample-source-in-position-x-and-limelight-interface-settings/4639 "2019-04-30T06:21:20Z")\
**Posts on this page:** 2\
**Page:** 1

<div class="post-metadata">

**Author:** ![EnthuMan](https://avatars.discourse-cdn.com/v4/letter/e/f1d935/32.png) [@EnthuMan](https://discourse.myriadrf.org/u/EnthuMan)\
**Post date:** [30 April 2019 06:21 UTC](https://discourse.myriadrf.org/t/what-is-frame-sample-source-in-position-x-and-limelight-interface-settings/4639/1 "2019-04-30T06:21:20Z")

</div>

Hello @Zack  
This is with reference to the terminology in the Programming guide and the connection to the waveforms in the datasheet.  
There is the use of the word “Frame” which I am unable to trace.

1. Reg 0x0023, LMLx\_FIDM: **frame start ID selection**. What does this mean?

2. Reg 0x0024, Sample source in positions 0,1,2,3. Where are these positions defined?  
Is the TRXIQPULSE mode same as JESD 207 mode?

3. From the FPGA code I understood that there are four modes of operation of the limelight interface:  
1) SISO\_DDR  
2) SISO\_SDR  
3) MIMO\_DDR  
4) PULSE\_DDR  
Please advise on how are these configured.  
3.1) Register 0x0022, LMLx\_SISODDR (DDR mode off/on). Does turning it OFF enable SISO\_SDR mode ON?  
3.2) How is MIMO\_DDR mode enabled (does turning OFF TRXIQPULSE mode off enable MIMO\_DDR)?  
3.3) Could you please provide the waveform for SISO\_DDR mode? My understanding is the following:  
Figs 33-36: are PULSE\_DDR/JESD 207 mode  
Figs 37-38: are MIMO-DDR mode which is same as TRXIQ DDR mode  
Figs 39-40: are SISO-SDR mode

Thanks as always for your time and help,

---

<div class="post-metadata">

**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [2 May 2019 12:57 UTC](https://discourse.myriadrf.org/t/what-is-frame-sample-source-in-position-x-and-limelight-interface-settings/4639/2 "2019-05-02T12:57:12Z")

</div>

Hi @EnthuMan,

> [@EnthuMan](#):
>
> 1. Reg 0x0023, LMLx\_FIDM: **frame start ID selection**. What does this mean?

It lets you know when new data frame starts. Actually, it defines ENABLE\_IQ\_SEL signal behavior. If LMLx\_FIDM is set to 0, then ENABLE\_IQ\_SEL signal will be low when new data frame starts. For instance, let us assume LMS7 sends this sequence of IQ data:  
AI0, AQ0, BI0, BQ0, AI1, AQ1, BI1, BQ1, …  
If LMLx\_FIDM is set to 0, then ENABLE\_IQ\_SEL will be low when AI0, AQ0 and AI1, AQ1 and high when BI0, BQ0 and BI1, BQ1  
In the case above, it actually identifies MIMO A or MIMO B channel.

> [@EnthuMan](#):
>
> Reg 0x0024, Sample source in positions 0,1,2,3. Where are these positions defined?

Assume IQ data frame from example above: AI0, AQ0, BI0, BQ0. Register 0x0024, bits [8:15] defines sample position in this sequence. If these are kept as default, then sequence will be AI, AQ, BI, BQ. If you set LML1\_SxS[1:0] registers to 0, then frame will be as follows: AI, AI, AI, AI (not very useful, just as an example).  
Another example. Let us set:  
LML1\_S0S[1:0] = 11  
LML1\_S1S[1:0] = 10  
LML1\_S2S[1:0] = 01  
LML1\_S3S[1:0] = 00  
Then IQ data frame sequence will be: BQ, BI, AQ, AI.

> [@EnthuMan](#):
>
> Is the TRXIQPULSE mode same as JESD 207 mode?

No, it is more like TRXIQ. The difference is in ENABLE\_IQ\_SEL duration only. In TRXIQ mode ENABLE\_IQ\_SEL duration length is 2 samples, while in TRXIQPULSE mode ENABLE\_IQ\_SEL duration length is 1 sample.

> [@EnthuMan](#):
>
> From the FPGA code I understood that there are four modes of operation of the limelight interface:
> 
> 1. SISO\_DDR
> 2. SISO\_SDR
> 3. MIMO\_DDR
> 4. PULSE\_DDR  
> Please advise on how are these configured.

Check this document for more information:

> <https://github.com/myriadrf/LMS7002M-docs/blob/master/LimeLight_modes_description_v01r01.pdf>