Hello, does anyone has the encountered the following error message:
“ERROR: Too many blocks”
I must have updated the USB LimeSDR that I was having and now i cannot longer work with it either on Gnuradio companion (3.10.5.1) nor on LimeSuiteGUI.
This error keeps popping up continuously.
I have the following Lime SDR:
[LimeSDR-USB, media=USB 3.0, module=FX3, addr=1d50:6108, serial=0009081C05C1302A]
Thank you.
“ERROR: Too many blocks” code is returned by the device, if the control packet header specified that it contains more data than can fit inside packet.
Assuming the software was not modified, then it should not happen. Or perhaps the device is returning bad data and it just gets interpreted wrong.
You can enable “log data” in right lower corner of LimeSuiteGUI to see what’s being written and read from the device.
Thank you very much for your fast reply.
I tried to test various older software versions including the ones found here index - powered by h5ai v0.29.1 (https://larsjung.de/h5ai/)
After the last one I have new issues:
Now I cannot install any more the FW and FPGA from the latest version - 22.09 
The error messages now do not include no more the message “Too many blocks”.
If you could propose anything to revert the situation I would be willing to try.
I share the new error messages:
[17:56:41] INFO: Disconnected control port
[17:56:47] ERROR: TransferPacket: Read failed (ret=0)
[17:56:47] WARNING: Gateware version mismatch!
Expected gateware version 1, revision 20
But found version 0, revision 0
Follow the FW and FPGA upgrade instructions:
Lime Suite - Myriad-RF Wiki
Or run update on the command line: LimeUtil --update
[17:56:47] INFO: CLK0 fOut = 27 MHz Multisynth Divider 33 0/1 R divider = 1 source = PLLA
[17:56:47] INFO: CLK1 fOut = 27 MHz Multisynth Divider 33 0/1 R divider = 1 source = PLLA
[17:56:47] INFO: CLK2 fOut = 27 MHz Multisynth Divider 8 0/1 R divider = 1 source = PLLA
[17:56:47] INFO: CLK3 fOut = 27 MHz Multisynth Divider 8 0/1 R divider = 1 source = PLLA
[17:56:47] INFO: CLK4 fOut = 27 MHz Multisynth Divider 8 0/1 R divider = 1 source = PLLA
[17:56:47] INFO: CLK5 fOut = 27 MHz Multisynth Divider 8 0/1 R divider = 1 source = PLLA
[17:56:47] INFO: CLK6 fOut = 27 MHz Multisynth Divider 8 0/1 R divider = 1 source = PLLA
[17:56:47] INFO: CLK7 fOut = 27 MHz Multisynth Divider 8 0/1 R divider = 1 source = PLLA
[17:56:47] INFO: Si5351C: VCOA = 891 MHz Feedback Divider 35 41943/65536
[17:56:47] INFO: Si5351C: VCOB = 891 MHz Feedback Divider 35 41943/65536
[17:56:47] ERROR: TransferPacket: Read failed (ret=0)
[17:56:47] ERROR: TransferPacket: Write failed (ret=0)
[17:56:47] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] ERROR: TransferPacket: Write failed (ret=0)
[17:56:51] INFO: Connected Control port: LimeSDR-USB FW:3 HW:0 Protocol:1 GW:0.0 Ref Clk: -0.00 MHz
[17:57:55] INFO: Wr(64): (00 x 64 times)
[17:57:55] INFO: Rd(64): 00 01 00 00 00 00 00 00 03 0e 01 02 01 00 00 00 00 00 00 09 08 1c 05 c1 30 2a (00 x 38 times)
[17:57:59] ERROR: Programming failed! Error
It seems the board is functioning and info query through USB’s control endpoint is working. But other commands through bulk endpoint is not responding. So it most likely has wrong FPGA gateware installed.
What is your board’s version, that is printed somewhere on the edge of the board?
It must be 1.4s.
I tried to install the 1.4 FPGA program on LimeSuiteGUI but I cannot program it unfortunately with the latest version.
Then it’s the USB firmware that is wrong, because now it reports not 1.4.
And so automatic update will not pick the right files.
Try reprogram FX3 Flash using LimeSuiteGUI programming, and use this firmware file: https://downloads.myriadrf.org/project/limesuite/22.09/LimeSDR-USB_HW_1.4_r4.0.img
Then after power cycling the board it should show up as “LimeSDR-USB FW:4 HW:4”
Then either automatic update should work or you can manually program FPGA FLASH with this gateware file: https://downloads.myriadrf.org/project/limesuite/22.09/LimeSDR-USB_HW_1.4_r2.23.rbf
Then after power cycling the board it should work as expected.
Thank you very much!
After the above Flash updates I was able to revert back to the old “Too many blocks” issue.
Now the log every time I connect is the following:
[19:12:19] ERROR: Too many blocks
[19:12:19] WARNING: Gateware version mismatch!
Expected gateware version 2, revision 23
But found version 0, revision 0
Follow the FW and FPGA upgrade instructions:
Lime Suite - Myriad-RF Wiki
Or run update on the command line: LimeUtil --update
[19:12:19] ERROR: Too many blocks
[19:12:19] ERROR: Too many blocks
[19:12:19] INFO: Wr(64): (00 x 64 times)
[19:12:19] INFO: Rd(64): 00 01 00 00 00 00 00 00 04 0e 01 04 01 00 00 00 00 00 00 09 08 1c 05 c1 30 2a (00 x 38 times)
[19:12:19] INFO: Wr(64): 56 00 04 00 00 00 00 00 00 00 00 01 00 02 00 03 (00 x 48 times)
[19:12:19] INFO: Rd(64): 56 01 04 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00 0c (00 x 44 times)
[19:12:19] INFO: Connected Control port: LimeSDR-USB FW:4 HW:0 Protocol:1 GW:0.12 Ref Clk: -0.00 MHz
Ok, now the communications are working, but something is still not right with the FPGA. There should be nothing that could trigger “too many blocks” error before the first “INFO: Wr(64): (00 x 64 times)”. Are you using latest LimeSuite?
Thank you very much for your message.
I am using the LimeSuite version: 22.09.1-myriadrf1~ubuntu20.04
I can add the message from the LimeQuickTest
[ TESTING STARTED ]
->Start time: Fri Feb 10 22:00:25 2023
->LimeSuite version: 22.09.1-myriadrf1~ubuntu20.04
Gateware version mismatch!
Expected gateware version 2, revision 23
But found version 260, revision 0
Follow the FW and FPGA upgrade instructions:
Lime Suite - Myriad-RF Wiki
Or run update on the command line: LimeUtil --update
->Device: LimeSDR-USB, media=USB 3.0, module=FX3, addr=1d50:6108, serial=0009081C05C1302A, HW=0, GW=0.12
Serial Number: 0009081C05C1302A
Temperature internal ADC calibration failed
Chip temperature: 0 C
[ Clock Network Test ]
->FX3 GPIF clock test
Test Timeout. Last result: 0
->FX3 GPIF clock test FAILED
->Si5351C test
Test Timeout. Last result: 0
FAILED
->ADF4002 Test
Result: 0 - FAILED
FAILED
->VCTCXO test
Test Timeout. Last result: 0
FAILED
->Clock Network Test FAILED
[ FPGA EEPROM Test ]
->Read EEPROM
->Read data: 13 02 19 13 02 19 02
->FPGA EEPROM Test PASSED
[ LMS7002M Test ]
->Perform Registers Test
RegistersTestInterval(startAddr=0x82, endAddr=0x82) - failed
RegistersTestInterval(startAddr=0x84, endAddr=0x84) - failed
RegistersTestInterval(startAddr=0x85, endAddr=0x85) - failed
RegistersTestInterval(startAddr=0x86, endAddr=0x8c) - failed
RegistersTestInterval(startAddr=0xa8, endAddr=0xac) - failed
RegistersTestInterval(startAddr=0xa8, endAddr=0xac) - failed
RegistersTestInterval(startAddr=0xad, endAddr=0xae) - failed
RegistersTestInterval(startAddr=0xad, endAddr=0xae) - failed
RegistersTestInterval(startAddr=0x100, endAddr=0x104) - failed
RegistersTestInterval(startAddr=0x100, endAddr=0x104) - failed
RegistersTestInterval(startAddr=0x105, endAddr=0x10b) - failed
RegistersTestInterval(startAddr=0x105, endAddr=0x10b) - failed
RegistersTestInterval(startAddr=0x10c, endAddr=0x114) - failed
RegistersTestInterval(startAddr=0x10c, endAddr=0x114) - failed
RegistersTestInterval(startAddr=0x115, endAddr=0x11a) - failed
RegistersTestInterval(startAddr=0x115, endAddr=0x11a) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x11c, endAddr=0x124) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x200, endAddr=0x20c) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x240, endAddr=0x261) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x280, endAddr=0x2a7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x2c0, endAddr=0x2e7) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x300, endAddr=0x327) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x340, endAddr=0x367) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x380, endAddr=0x3a7) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x400, endAddr=0x40f) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x440, endAddr=0x461) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x480, endAddr=0x4a7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x4c0, endAddr=0x4e7) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x500, endAddr=0x527) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x540, endAddr=0x567) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x580, endAddr=0x5a7) - failed
RegistersTestInterval(startAddr=0x20, endAddr=0x2f) - failed
RegistersTestInterval(startAddr=0x20, endAddr=0x2f) - failed
RegistersTestInterval(startAddr=0x92, endAddr=0xa7) - failed
RegistersTestInterval(startAddr=0x92, endAddr=0xa7) - failed
RegistersTest() failed
->LMS7002M Test FAILED
[ RF Loopback Test ]
Note: The test should be run without anything connected to RF ports
->Configure LMS
TuneVCO(CGEN) - failed to lock (cmphl!=0)
SetFrequencyCGEN(61.44 MHz) failed
TuneVCO(CGEN) - failed to lock (cmphl!=0)
SetFrequencyCGEN(491.52 MHz) failed
Failed to set sample rate
->RF Loopback Test FAILED
=> Board tests FAILED <=
Elapsed time: 4.06 seconds
Is it possible that the board is somehow damaged?
Please let me know if I could give any further information or if you believe that further analysis should not be performed on the board
All register writes and reads are suppose to go through FPGA so all the tests most likely fail if the FPGA is not working correctly.
The “Too many blocks” error can only be returned from USB microcontroller LimeSDR-USB_FX3/main.c, so bad FPGA would not cause it. Either the software is sending bad packet, or the USB microcontroller is receiving corrupted data, but it’s unlikely because this shows normal behavior, except the registers data that is returned from FPGA:
[19:12:19] INFO: Wr(64): 56 00 04 00 00 00 00 00 00 00 00 01 00 02 00 03 (00 x 48 times)
[19:12:19] INFO: Rd(64): 56 01 04 00 00 00 00 00 00 00 00 0c 00 00 00 00 00 00 00 0c (00 x 44 times)
It’s possible that the board could draw more current from the USB port than the port can supply, and it would cause a brownout, resulting in undefined behaviour. You could try using the board with external power supply, or just try using it on different PC or USB port.
Hello,
Sorry for the long time to reply.
Unfortunately by changing USB ports or using an external power supply there is no change in the behavior of the LimeSDR.
Would you suggest any other test, or other version of SW to load?
How could I make a test to exclude any parts of the SDR to be damaged?
e.g. Is there any test only for the FPGA, only for any flash memory?
Perhaps I could try to load a specif version of the FPGA firmware which is more basic or stable?