KarlL
5 April 2018 01:03
2
Check Synchronize two LimeSDR , especially
Not sure how lively this thread is, but I was wanting something along the lines of the PPS reset of the timestamps discussed above, and did make a small change to the FPGA to do it. On the top level of the FPGA source (lms7_trx_top.bdf) I disconnected lte_clr_smpl_nr from the rx_path_top block. Then added an OR gate. The output of the OR goes to the clr_smpl_nr input of rx_path_top, the inputs of the OR come from lte_clr_smpl_nr and from FPGA_GPIO[0]. So now I can reset the timestamps with a pul…
where a timestamp reset is done through GPIO. This does require a modification in the gateware but it’s quite limited. cmichal even posted the binary gateware here:
What you describe is basically right -toggling the GPIO high then low will reset the timestamp counter, and you detect it by seeing that the most recent timestamp is lower than the one before. I think if you see a timestamp of 0 you shouldn’t trust it, because it probably gets held at zero as long as the GPIO is high, so look at the timestamp of the next packet.
I think the only source file that’s changed is the top level bdf. I’ve put mine at http://www.phas.ubc.ca/~michal/lms7_trx_top.bdf , an…
HTH
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