# This is good news -- RISC V CPU core for LimeSDR

**URL:** <https://discourse.myriadrf.org/t/this-is-good-news-risc-v-cpu-core-for-limesdr/1192>\
**Category:** LimeSDR\
**Created:** [4 May 2017 23:44 UTC](https://discourse.myriadrf.org/t/this-is-good-news-risc-v-cpu-core-for-limesdr/1192 "2017-05-04T23:44:27Z")\
**Posts on this page:** 8\
**Page:** 1

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**Author:** ![hTo137](https://avatars.discourse-cdn.com/v4/letter/h/ba8739/32.png) [@hTo137](https://discourse.myriadrf.org/u/hTo137)\
**Post date:** [4 May 2017 23:44 UTC](https://discourse.myriadrf.org/t/this-is-good-news-risc-v-cpu-core-for-limesdr/1192/1 "2017-05-04T23:44:27Z")

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The project is moving ahead.

[https://fossi-foundation.org/2017/05/04/gsoc](https://fossi-foundation.org/2017/05/04/gsoc)

One question to @andrewback, do we also get the FuseSoC development tools as a bonus as part of this work?

Congrats to the student Cairo Caplan too! Thanks to the mentors too.

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**Author:** ![andrewback](https://avatars.discourse-cdn.com/v4/letter/a/22d042/32.png) [@andrewback](https://discourse.myriadrf.org/u/andrewback)\
**Post date:** [5 May 2017 07:51 UTC](https://discourse.myriadrf.org/t/this-is-good-news-risc-v-cpu-core-for-limesdr/1192/2 "2017-05-05T07:51:50Z")

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They were two separate project ideas, but it does look that way.

It’s very exciting indeed and looking forward to LimeSDR with RISC-V + FuseSoC 🕶

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**Author:** ![hTo137](https://avatars.discourse-cdn.com/v4/letter/h/ba8739/32.png) [@hTo137](https://discourse.myriadrf.org/u/hTo137)\
**Post date:** [6 May 2017 01:00 UTC](https://discourse.myriadrf.org/t/this-is-good-news-risc-v-cpu-core-for-limesdr/1192/3 "2017-05-06T01:00:16Z")

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Looking forward to this. It seems ambitious but with three mentors that should make it move along.

Let us know if there’s testing or something we can do here.

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**Author:** ![cairo.caplan](https://avatars.discourse-cdn.com/v4/letter/c/dfb087/32.png) [@cairo.caplan](https://discourse.myriadrf.org/u/cairo.caplan)\
**Post date:** [26 May 2017 10:10 UTC](https://discourse.myriadrf.org/t/this-is-good-news-risc-v-cpu-core-for-limesdr/1192/4 "2017-05-26T10:10:43Z")

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> [@andrewback](#):
>
> citing indeed and looking forward to LimeSDR with RISC-V + FuseSoC 🕶

Hello!

Thank you @andrewback ,  
So here I present myself, my name is Cairo. I am working on the port of RISC V CPUs and FuseSoC integration of the LimeSDR gateware. Currently I am a PhD student in Aix-Marseille and I have some time of experience on FPGA programming. For long I have interest to work with a open source CPU project and I find amazing the concept of SDR in hardware, as allowed by LimeSDR with its FPRF ASIC.

I have picked three flavors open sources RISC V CPUs that are FPGA friendly to test, which I want to profit as they can share the same Instructions Set and software tools.  
Orca - [https://github.com/VectorBlox/orca](https://github.com/VectorBlox/orca) ,  
Pulpino - [pulpino/fpga at master · pulp-platform/pulpino · GitHub](https://github.com/pulp-platform/pulpino/tree/master/fpga)  
picorv32 - [GitHub - YosysHQ/picorv32: PicoRV32 - A Size-Optimized RISC-V CPU](https://github.com/cliffordwolf/picorv32)

As soon as I get the first of them working my focus will turn on how to make the system FuseSoC friendly.

My work will be published on the riscv branch of LimeSDR Gateware repository on GitHub

> **[GitHub - myriadrf/LimeSDR-USB\_GW at riscv](https://github.com/myriadrf/LimeSDR-USB_GW/tree/riscv)**
>
> riscv

Soon I will give the link of a blog where I am writing my experiences with the setup and the project.

I accept suggestions and help, my contact is [cairorj@gmail.com](mailto:cairorj@gmail.com) .  
Wish me luck!

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**Author:** ![martywittrock](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/martywittrock/32/66_2.png) [@martywittrock](https://discourse.myriadrf.org/u/martywittrock)\
**Post date:** [26 May 2017 13:13 UTC](https://discourse.myriadrf.org/t/this-is-good-news-risc-v-cpu-core-for-limesdr/1192/5 "2017-05-26T13:13:50Z")

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Cairo,

We not only wish you luck, but we’re inspired by what you’re off to contribute to the Lime community.

Onward and upward…!

73 de Marty, KN0CK

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**Author:** ![hTo137](https://avatars.discourse-cdn.com/v4/letter/h/ba8739/32.png) [@hTo137](https://discourse.myriadrf.org/u/hTo137)\
**Post date:** [28 May 2017 18:07 UTC](https://discourse.myriadrf.org/t/this-is-good-news-risc-v-cpu-core-for-limesdr/1192/6 "2017-05-28T18:07:02Z")

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Good luck!!! ☘

We are lucky to have you. I think it’s an exciting project and look forward to seeing it all unfold. Just seems like a really good and exciting summer project.

If you think there’s someway that I can help with testing or anything else related to this project just ask. The worst thing I can say is no but I will try to say yes.

Also, in this here US of A, a PhD candidate usually has a 4 year degree (sometimes in less than 4 years) and a 2 year Masters degree and then they begin working on their PhD. I have heard things are different in Germany for example. How does it work where you are? I hope this is not too personal. I only ask so we all learn something.

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**Author:** ![cairo.caplan](https://avatars.discourse-cdn.com/v4/letter/c/dfb087/32.png) [@cairo.caplan](https://discourse.myriadrf.org/u/cairo.caplan)\
**Post date:** [31 May 2017 13:12 UTC](https://discourse.myriadrf.org/t/this-is-good-news-risc-v-cpu-core-for-limesdr/1192/7 "2017-05-31T13:12:40Z")

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> [@hTo137](#):
>
> g project and look forward to seeing it all unfold. Just seems like a really good and exciting summer project.
> 
> If you think there’s someway that I can help with testing or anything else related to this project just ask. The worst thing I can say is no but I will try to say yes.

Thank you 🙂 Sure!

Haha, this goes offtopic. I know in France the equivalent of a BSc+Master sums 5 years and a PhD 3 years. In Brazil where I am from, for engineers at least, you do 5 years for BSc, 2 years for Master and 4 for PhD, but is common to see people, including univ professors, to spend way more time.

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**Author:** ![hTo137](https://avatars.discourse-cdn.com/v4/letter/h/ba8739/32.png) [@hTo137](https://discourse.myriadrf.org/u/hTo137)\
**Post date:** [3 June 2017 00:57 UTC](https://discourse.myriadrf.org/t/this-is-good-news-risc-v-cpu-core-for-limesdr/1192/8 "2017-06-03T00:57:33Z")

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@cairo.caplan that’s a lot of studying. Maybe this project is good way to do something similar but different enough to be some fun.