modimo
21 December 2017 08:24
6
will_mysky:
If this is an unresolved issue that there is no support for, I will be abandoning the hardware immediately. How can this not have been addressed by now? I feel like I’m missing something here, as from looking at the block diagrams both receivers are fed from a common oscillator source so I don’t know how this is happening other than the chip is dropping phase trim values between operations?
My best guess is ADC misalignment. Resetting of register does not help. Since your demo is in GNU radio maybe someone will take a closer look since it is easy to reproduce. I think it will be useful if you will post sample project.
Is it possible to maitain channel alignment between channels A and B? It seems that there is time shift between channels (it can be seen as linear phase difference). From what i experienced it is connected with decimation block. Depending on decimation ratio the time shift has different “resolution”. For example if decimation ratio is 8 then time misalignment occurs in multiples 1/8th of output sample time Ts. If decimation ratio is 16 te misalignment is in 1/16th of Ts. It seems that counter wi…
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