# Sample rate calculations

**URL:** <https://discourse.myriadrf.org/t/sample-rate-calculations/2575>\
**Category:** LimeSDR\
**Created:** [4 April 2018 02:20 UTC](https://discourse.myriadrf.org/t/sample-rate-calculations/2575 "2018-04-04T02:20:28Z")\
**Posts on this page:** 6\
**Page:** 1

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**Author:** ![mleech](https://avatars.discourse-cdn.com/v4/letter/m/34f0e0/32.png) [@mleech](https://discourse.myriadrf.org/u/mleech)\
**Post date:** [4 April 2018 02:20 UTC](https://discourse.myriadrf.org/t/sample-rate-calculations/2575/1 "2018-04-04T02:20:28Z")

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So, I would like to know how sample rates “work” in the LimeSDR. The master clock is at 30.72MHz, from the messages I get during start-up, but through Soapy/gr-osmosdr, I can  
ask for sample-rates that aren’t integer fractions of the master-clock. I don’t get any error messages.

So, does something “underneath” change the master-clock rate? Is there a fractional resampler in the FPGA? Does it just not give error messages for “impossible” sample-rates?

Inquiring minds want to know, etc, etc.

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [4 April 2018 05:36 UTC](https://discourse.myriadrf.org/t/sample-rate-calculations/2575/2 "2018-04-04T05:36:28Z")

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30.72MHz is just a reference clock for PLLs inside of LMS7002M chip. PLLs inside of LMS7002M can generate desired (well, there is a range, of course) frequencies for you.

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**Author:** ![mleech](https://avatars.discourse-cdn.com/v4/letter/m/34f0e0/32.png) [@mleech](https://discourse.myriadrf.org/u/mleech)\
**Post date:** [4 April 2018 17:36 UTC](https://discourse.myriadrf.org/t/sample-rate-calculations/2575/3 "2018-04-04T17:36:08Z")

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Thanks, Zack.

So another, related question is how is the filter+decimation “distributed” in the design–is it  
all done in the LMS chip, or is there also the usual CIC decimator (or similar) in the FPGA?

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [5 April 2018 07:15 UTC](https://discourse.myriadrf.org/t/sample-rate-calculations/2575/4 "2018-04-05T07:15:54Z")

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Hi @mleech,

It is all done in LMS7002M. No additional filters in FPGA. Check digital path structures in Figure 11 & 12 in [LMS7002M datasheet](https://github.com/myriadrf/LMS7002M-docs/blob/master/LMS7002M_Data_Sheet_v3.1r00.pdf).

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**Author:** ![mleech](https://avatars.discourse-cdn.com/v4/letter/m/34f0e0/32.png) [@mleech](https://discourse.myriadrf.org/u/mleech)\
**Post date:** [5 April 2018 18:43 UTC](https://discourse.myriadrf.org/t/sample-rate-calculations/2575/5 "2018-04-05T18:43:08Z")

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OK, so in the “factory” FPGA image, there’s isn’t much DSP going on in there, I gather…

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [9 April 2018 05:49 UTC](https://discourse.myriadrf.org/t/sample-rate-calculations/2575/6 "2018-04-09T05:49:05Z")

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Hi @mleech,

That’s correct. No DSP functions in FPGA.