You could indeed have a loop, where you call RecvStream, then check the timestamp. If it’s negative, then it means the synchronization signal was received (see again Synchronize two LimeSDR).
So at first you just drop all received samples with positive timestamps, then once you receive a negative timestamp, you know it’s the start of the signal your interested in. Then depending on what you need to do with that signal, you either process the samples live, or you can receive all the X following samples in a big enough buffer, and then process them.
Note that the timestamp is for a block of 1360 samples (in mono channel) or 680 samples (in dual channel). This has to do with how the FPGA is programmed. You need to see if that precision is good enough for what you need.
If you don’t care about the real timestamps, then it’s fine. If you do need the real timestamps, then you’ll need to deduce the start of your signal depending on the previous or following positive timestamps.
You won’t get duplicate or incomplete samples. If you ask RecvStream to return eg 1000 samples, it won’t return until it has 1000 new samples.