# Required mPCIe data signals for LimeSDR XTRX

**URL:** <https://discourse.myriadrf.org/t/required-mpcie-data-signals-for-limesdr-xtrx/8008>\
**Category:** LimeSDR\
**Created:** [1 August 2023 06:51 UTC](https://discourse.myriadrf.org/t/required-mpcie-data-signals-for-limesdr-xtrx/8008 "2023-08-01T06:51:15Z")\
**Posts on this page:** 1\
**Showing post:** 8

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**Author:** ![sergey](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/sergey/32/4871_2.png) [@sergey](https://discourse.myriadrf.org/u/sergey)\
**Post date:** [21 May 2025 09:01 UTC](https://discourse.myriadrf.org/t/required-mpcie-data-signals-for-limesdr-xtrx/8008/8 "2025-05-21T09:01:16Z")

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> Thank you very much for your reply. Had a look at the mPCIe edge connector pin definition in Table 16, it seems to be a standard 1x lane mPCIe pin arrangement. Do I miss anything here? Could you please help me on the 2 lanes wiring aspect?

There are `PCI_TX1_N`, `PCI_TX1_P`, `PCI_RX1_N`, and `PCI_RX1_P` on pins 39, 41, 47, and 49. I think those are not very standard, but are used on some of the embedded systems.

> I am considering connecting it with a computer board with a mPCIe interface for I Q sample streaming at around 120MB/s. Is there any tricky aspect I need to pay attention to?

I _think_ you should be fine with a single PCIe lane for 120MB/s, as a single gen2 lane supports 500MB/s (in each direction).

There are some numbers Ricardas mentioned in this post: [Some tech questions about the LimeSDR XTRX ecosystem - #3 by ricardas](https://discourse.myriadrf.org/t/some-tech-questions-about-the-limesdr-xtrx-ecosystem/8632/3)

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