# Phase Locking Problem

**URL:** <https://discourse.myriadrf.org/t/phase-locking-problem/6838>\
**Category:** LimeSDR\
**Created:** [9 January 2021 09:39 UTC](https://discourse.myriadrf.org/t/phase-locking-problem/6838 "2021-01-09T09:39:16Z")\
**Posts on this page:** 4\
**Page:** 1

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**Author:** ![ugy99](https://avatars.discourse-cdn.com/v4/letter/u/ecccb3/32.png) [@ugy99](https://discourse.myriadrf.org/u/ugy99)\
**Post date:** [9 January 2021 09:39 UTC](https://discourse.myriadrf.org/t/phase-locking-problem/6838/1 "2021-01-09T09:39:16Z")

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Hello,  
I am trying to demodulate a simple standart AM signal that is in the form (1+sin(2π1000t))sin(2π30e6t+Φ) using LimeSuite API. This means 30MHz sine wave carrier and 1kHz sine wave message. I am using two synchronized signal generators, one being a reference clock input and the other one generating the AM signal. Since AM modulation is essentially the same as IQ modulation but the Q part is equal to zero, I should only see the noise as the Q part. The problem is neither I nor Q is zero but they are sine waves with random amplitude on every run. This means that the the carrier wave and LO signal is not in phase even though I use a reference clock. How can I make them in phase? Doesn’t limeSDR supposed have phase detectors and correctors?

By the way, without the reference clock, the output is a total meaningless mess, I would expect a better result this way also.

Thanks in advance for your replies.

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**Author:** ![ugy99](https://avatars.discourse-cdn.com/v4/letter/u/ecccb3/32.png) [@ugy99](https://discourse.myriadrf.org/u/ugy99)\
**Post date:** [10 January 2021 12:59 UTC](https://discourse.myriadrf.org/t/phase-locking-problem/6838/2 "2021-01-10T12:59:20Z")

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Really, can anybody on this forum help me on this issue? I’ve read the datasheet thoroughly and could not find a solution anywhere else.

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**Author:** ![RightHalfPlane](https://avatars.discourse-cdn.com/v4/letter/r/46a35a/32.png) [@RightHalfPlane](https://discourse.myriadrf.org/u/RightHalfPlane)\
**Post date:** [11 January 2021 15:01 UTC](https://discourse.myriadrf.org/t/phase-locking-problem/6838/3 "2021-01-11T15:01:42Z")

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To generate a pure “I” signal you need input two signals exactly in phase at fc + w and fc - w or perhaps you can jumper it in at some point on the board.

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**Author:** ![alpemresahin](https://avatars.discourse-cdn.com/v4/letter/a/cab0a1/32.png) [@alpemresahin](https://discourse.myriadrf.org/u/alpemresahin)\
**Post date:** [12 January 2021 13:15 UTC](https://discourse.myriadrf.org/t/phase-locking-problem/6838/4 "2021-01-12T13:15:01Z")

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I have a similar problem with an IQ modulated signal. How do we control phase locking?