# Phase jumps while transmitting DC signal

**URL:** <https://discourse.myriadrf.org/t/phase-jumps-while-transmitting-dc-signal/2003>\
**Category:** LimeSDR\
**Created:** [14 November 2017 09:38 UTC](https://discourse.myriadrf.org/t/phase-jumps-while-transmitting-dc-signal/2003 "2017-11-14T09:38:48Z")\
**Posts on this page:** 6\
**Page:** 1

<div class="post-metadata">

**Author:** ![DreamNik](https://avatars.discourse-cdn.com/v4/letter/d/898d66/32.png) [@DreamNik](https://discourse.myriadrf.org/u/DreamNik)\
**Post date:** [14 November 2017 09:38 UTC](https://discourse.myriadrf.org/t/phase-jumps-while-transmitting-dc-signal/2003/1 "2017-11-14T09:38:48Z")

</div>

Hi!

I’ve run into this sutuation.

While transmitting DC signal (I=const, Q=const) from TSG or digital interface, received signal (as measured by LimeSDR and external spectrum analyzer) have phase jumps, like in phase modulated signal.

Here is phase jump:

 ![1](https://yyz2.discourse-cdn.com/flex034/uploads/myriadrf/original/2X/c/c8d92119996cfa9f2182d82e86bff837b3e6b41d.png)

After I’ve changed TBB gain, this process started to alternate. For example, 1 second with multiple jumps, another second without jumps.  
After running for a while, jumps completely gone.

Jumps after changing gain:

 ![3](https://yyz2.discourse-cdn.com/flex034/uploads/myriadrf/original/2X/4/42a051cd46ef50065975c21f79e5ab867fe1e7a9.png)

No jumps, after running for some minutes.

 ![2](https://yyz2.discourse-cdn.com/flex034/uploads/myriadrf/original/2X/6/6b66b3478b0fb883aa02b5f3954abfc7b29b243d.png)

At first, it looked like some DAC bit is getting out-of-clock at digital interface.  
But even using TxTSG problems remains.  
Happened mutiple times, with different sample rates, different gains and at different frequencies (2 - 3 GHz band).

---

<div class="post-metadata">

**Author:** ![Zero](https://avatars.discourse-cdn.com/v4/letter/z/a88e57/32.png) [@Zero](https://discourse.myriadrf.org/u/Zero)\
**Post date:** [14 November 2017 11:50 UTC](https://discourse.myriadrf.org/t/phase-jumps-while-transmitting-dc-signal/2003/2 "2017-11-14T11:50:06Z")

</div>

I’ve seen something about this sort of thing before - could it be the DC bias correction kicking in at inopportune times?

There’s a way to tell the board to stop the DC correction algorithm via the API; you might give that a try.

---

<div class="post-metadata">

**Author:** ![ricardas](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/ricardas/32/86_2.png) [@ricardas](https://discourse.myriadrf.org/u/ricardas)\
**Post date:** [14 November 2017 14:13 UTC](https://discourse.myriadrf.org/t/phase-jumps-while-transmitting-dc-signal/2003/3 "2017-11-14T14:13:44Z")

</div>

What are Tx/Rx PLL frequencies? If they are very close together it could create problems

---

<div class="post-metadata">

**Author:** ![DreamNik](https://avatars.discourse-cdn.com/v4/letter/d/898d66/32.png) [@DreamNik](https://discourse.myriadrf.org/u/DreamNik)\
**Post date:** [14 November 2017 15:18 UTC](https://discourse.myriadrf.org/t/phase-jumps-while-transmitting-dc-signal/2003/4 "2017-11-14T15:18:19Z")

</div>

They’re same.

RX=2.9 GHz  
TX=2.9 GHz

(shifted from 2.4 GHz to eliminate Wi-Fi interference)

---

<div class="post-metadata">

**Author:** ![ricardas](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/ricardas/32/86_2.png) [@ricardas](https://discourse.myriadrf.org/u/ricardas)\
**Post date:** [14 November 2017 15:44 UTC](https://discourse.myriadrf.org/t/phase-jumps-while-transmitting-dc-signal/2003/5 "2017-11-14T15:44:41Z")

</div>

That’s the problem. Unless you are running in TDD mode, having both PLLs with the same frequency can produce effects such as this.

---

<div class="post-metadata">

**Author:** ![gwong](https://avatars.discourse-cdn.com/v4/letter/g/f17d59/32.png) [@gwong](https://discourse.myriadrf.org/u/gwong)\
**Post date:** [14 November 2017 16:01 UTC](https://discourse.myriadrf.org/t/phase-jumps-while-transmitting-dc-signal/2003/6 "2017-11-14T16:01:41Z")

</div>

Look here for the specific instructions to lock the SXR and SXT:

> [@\[LimeSDR-USB\] Synchronization and Toggle TDD/FDD Mode](https://discourse.myriadrf.org/t/limesdr-usb-synchronization-and-toggle-tdd-fdd-mode/1791/5):
>
> TDD mode for LMS7002M is activated via configuration. The idea is to use only one PLL (SXT) for both Rx and Tx chains. Here are steps on how to do it using LimeSuiteGUI: Starting setup is as a normal FDD mode (both RX and TX synthesizers are working). Set register 0x011C[6] = 0 while 0x0020[1:0] = 2 (or SXT tab is selected in LimeSuiteGUI - uncheck control check box called “LO buffer from SXT to SXR” under “Power down controls”). Set 0x011C[1] = 1 while 0x0020[1:0] = 1 (or SXR tab is selected…