@maedula If you read through the gateware source code for the PCIe ( https://github.com/myriadrf/LimeSDR-PCIe ), PCIe is achieved by using xillybus cores.
xillybus using “Altera Cyclone IV with 4x lanes” has a maximum RX+TX bandwidth of 400 MiB/sec which is explicitly allocated as 195MiB/s 32bit RX, 180MiB/s 32 bit TX and the rest looks like it is used for control communications.
So although PCIe(v1) x4 lanes has a theoretical maximum throughput of 1GiB/sec, only 400MiB/sec is possible using the xillybus cores. That is my reading of it, but I could be wrong.
But in future it could be faster - “higher-bandwidth revisions of Xillybus’ IP core will be rolling out during 2016”