# LMS7002M custom board bring-up

**URL:** <https://discourse.myriadrf.org/t/lms7002m-custom-board-bring-up/4529>\
**Category:** General Discussion\
**Created:** [12 April 2019 10:05 UTC](https://discourse.myriadrf.org/t/lms7002m-custom-board-bring-up/4529 "2019-04-12T10:05:43Z")\
**Posts on this page:** 6\
**Page:** 1

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**Author:** ![EnthuMan](https://avatars.discourse-cdn.com/v4/letter/e/f1d935/32.png) [@EnthuMan](https://discourse.myriadrf.org/u/EnthuMan)\
**Post date:** [12 April 2019 10:05 UTC](https://discourse.myriadrf.org/t/lms7002m-custom-board-bring-up/4529/1 "2019-04-12T10:05:43Z")

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Hello,  
We have built a custom board with the LMS7002M chip and are trying to establish SPI communication with the chip.  
For the same we are using the drivers provided on git. The SPI interface is running at around 8MHz and has been validated independent of the LMS interface.  
The chip version is being read as the first step. The procedure we are following is:

1. LMS\_RESET (low followed by high)
2. read 0x002F register  
We are unable to read anything.  
Questions:
3. Any help on getting this first step going
4. We are feeding a 50MHz clk on the rx\_pll\_clk pin of the LMS. Is the clock supposed to be fed on some other line? How does the LMS chip choose this clock for the uController running the SPI interface
5. How is the 3 wire or 4 wire interface chosen?

Thank you for time,

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**Author:** ![kishores](https://avatars.discourse-cdn.com/v4/letter/k/9f8e36/32.png) [@kishores](https://discourse.myriadrf.org/u/kishores)\
**Post date:** [12 April 2019 12:40 UTC](https://discourse.myriadrf.org/t/lms7002m-custom-board-bring-up/4529/2 "2019-04-12T12:40:16Z")

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We are facing similar issues . Use `LMS7002M_set_spi_mode(lms,4);
` to select 4 wire mode .

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [12 April 2019 13:08 UTC](https://discourse.myriadrf.org/t/lms7002m-custom-board-bring-up/4529/3 "2019-04-12T13:08:29Z")

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Hi @EnthuMan,

SPI is 4 wire after reset.  
I would suggest to refer to LimeSDR-USB or LimeSDR-Mini schematics.  
Clock should be fed to xoscin\_tx (E5) and xoscin\_rx (AM24) pins.  
What is CORE\_LDO\_EN (pin U33) level?

Could you paste SPI bus waveform with SCLK, SDIO, SDO SEN signals captured, please.

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**Author:** ![EnthuMan](https://avatars.discourse-cdn.com/v4/letter/e/f1d935/32.png) [@EnthuMan](https://discourse.myriadrf.org/u/EnthuMan)\
**Post date:** [12 April 2019 14:16 UTC](https://discourse.myriadrf.org/t/lms7002m-custom-board-bring-up/4529/4 "2019-04-12T14:16:00Z")

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Hello Zack,  
Thank you for your help.  
The waveforms as measured on the board are as follows:  
Legend:  
CH1 (yellow) is chip select  
CH2 : nothing  
CH3 (green) is MOSI  
CH4 (purple) is SCLK

 ![LMS1%20(Large)](https://canada1.discourse-cdn.com/flex034/uploads/myriadrf/original/2X/8/8fc9d45867f958c1fcbe488f407b3de3b46800be.jpeg)  
The above image is the capture of the complete communication (lms\_reset, lms\_set\_spi\_mode and lms\_spi\_reg\_read with the individual sections enclosed in red, blue and mustard rectangles respectively).  
We zoomed in and verified that the SPI settings were (mode 0) correct. Please ignore the difference in voltage levels (they are before and after a level shifter). As of now we are feeding a 50MHz clock (2.5V level) to the xoscin\_rx only (we understood that internally the clock can be shared with tx).  
The SDIO line remains high all the time.

The zoomed waveforms are the following:  
lms\_reset and lms\_set\_spi\_mode

 ![IMG_20190412_190503%20(Small)](https://canada1.discourse-cdn.com/flex034/uploads/myriadrf/original/2X/0/0f8b46af062b4a75a349967fae3710499bf66c63.jpeg)

lms\_spi\_read\_reg(0x002f) is three instructions (3 x 32clock cycles)  
the first two

 ![IMG_20190412_190517%20(Small)](https://canada1.discourse-cdn.com/flex034/uploads/myriadrf/original/2X/c/c7acf0186551d88ea89d3ea5abd579b5279ec5b4.jpeg)

the last one being

 ![IMG_20190412_190528%20(Small)](https://canada1.discourse-cdn.com/flex034/uploads/myriadrf/original/2X/a/a308c6697605e816e8e3a7f9f31cd66d27cbc53e.jpeg)

Our VDDIO\_LMS is set to 2.5V and CORE\_LDO\_EN is pulled high and set to 2.5V.

**Question:** What should be the current consumption of the LMS the first time without any programming or any EEPROM or anything at all? We are seeing close to zero current (read as: very little)

Thanks again,

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [15 April 2019 06:49 UTC](https://discourse.myriadrf.org/t/lms7002m-custom-board-bring-up/4529/5 "2019-04-15T06:49:48Z")

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> [@EnthuMan](#):
>
> **Question:** What should be the current consumption of the LMS the first time without any programming or any EEPROM or anything at all? We are seeing close to zero current (read as: very little)

It should consume in tents of mA. So, it looks like this is your issue. Are you sure LMS7002M is soldered properly?

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<div class="post-metadata">

**Author:** ![EnthuMan](https://avatars.discourse-cdn.com/v4/letter/e/f1d935/32.png) [@EnthuMan](https://discourse.myriadrf.org/u/EnthuMan)\
**Post date:** [17 April 2019 11:07 UTC](https://discourse.myriadrf.org/t/lms7002m-custom-board-bring-up/4529/6 "2019-04-17T11:07:25Z")

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You were right, there was a soldering problem. Thanks for your help.