# Link between RX and TX sampling rates

**URL:** <https://discourse.myriadrf.org/t/link-between-rx-and-tx-sampling-rates/4934>\
**Category:** LimeSDR\
**Created:** [11 July 2019 09:47 UTC](https://discourse.myriadrf.org/t/link-between-rx-and-tx-sampling-rates/4934 "2019-07-11T09:47:25Z")\
**Posts on this page:** 1\
**Showing post:** 3

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**Author:** ![IgnasJ](https://avatars.discourse-cdn.com/v4/letter/i/278dde/32.png) [@IgnasJ](https://discourse.myriadrf.org/u/IgnasJ)\
**Post date:** [24 July 2019 12:20 UTC](https://discourse.myriadrf.org/t/link-between-rx-and-tx-sampling-rates/4934/3 "2019-07-24T12:20:09Z")

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Hi,  
You may already know this, but ratio of sample rates in Tx and Rx is controlled by dividers and can only be power of 2 as described in LMS API ([https://github.com/myriadrf/LimeSuite/blob/master/src/lime/LimeSuite.h#L591](https://github.com/myriadrf/LimeSuite/blob/master/src/lime/LimeSuite.h#L591)).  
You can find more information about clock dividers for ADC and DAC in LMS datasheet:  
[https://wiki.myriadrf.org/LimeMicro:LMS7002M\_Datasheet#Data\_converters\_clock\_generation](https://wiki.myriadrf.org/LimeMicro:LMS7002M_Datasheet#Data_converters_clock_generation)  
In addition to ADC and DAC rates, Tx and Rx rates can be made different by setting different interpolations and decimation values in Tx TSP and Rx TSP modules.  
So when you ask for different samples rates, LimeSuite will adjust clock dividers and oversampling settings.  
Furthermore, on LimeSDR-Mini, setting Rx and Tx sample rate individually is completely disabled because of limitations in FPGA, so sample rate is always set for both.

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