18.03
Software version is good.
Try loading this config: https://www.dropbox.com/s/q6gc42jolfttm0z/MIMO.ini?dl=0
Press calculate in SXR, SXT and CGEN tabs. Try to calibrate A and then B channel. Both channels should succeed to calibrate properly.
Also just to make sure that correct MCU firmware is programmed into the chip (and not some leftover version from other software), reset the board before testing.
@ricardas I downloaded the configuration, the latest FPGA, FX3 images, compiled the latest LimeSuite source code from Github, installed the software, and programmed the device. I followed your instructions, however I’m still getting those MCU / loopback gain errors as shown in the logs below:
[11:43:13] INFO: Disconnected control port
[11:43:20] INFO: Reference clock 30.72 MHz
[11:43:20] INFO: Connected Control port: LimeSDR-USB FW:4 HW:4 Protocol:1 GW:2.16 Ref Clk: 30.72 MHz
[11:43:32] INFO: CGEN frequency set to 80.000000 MHz
[11:43:34] INFO: CGEN frequency set to 80.000000 MHz
[11:43:39] INFO: SXR frequency set to 1200.000000 MHz
[11:43:42] INFO: SXT frequency set to 1250.000000 MHz
[11:44:01] DEBUG: INT 77, FRAC 131072, DIV_OUTCH_CGEN 11
[11:44:01] DEBUG: VCO 2400.00 MHz, RefClk 30.72 MHz
[11:44:01] DEBUG: csw 169; interval [166, 173]
[11:44:01] DEBUG: M=208, N=4, Fvco=1300.000 MHz
[11:44:01] DEBUG: M=247, N=19, Fvco=1300.000 MHz
[11:44:05] DEBUG: INT 77, FRAC 131072, DIV_OUTCH_CGEN 11
[11:44:05] DEBUG: VCO 2400.00 MHz, RefClk 30.72 MHz
[11:44:05] DEBUG: csw 169; interval [166, 173]
[11:44:05] DEBUG: M=208, N=4, Fvco=1300.000 MHz
[11:44:05] DEBUG: M=247, N=19, Fvco=1300.000 MHz
[11:44:05] INFO: CGEN frequency set to 100.000000 MHz
[11:44:07] DEBUG: csw 170; interval [166, 174]
[11:44:07] DEBUG: M=208, N=4, Fvco=1300.000 MHz
[11:44:07] DEBUG: M=247, N=19, Fvco=1300.000 MHz
[11:44:08] DEBUG: INT 152, FRAC 262144, DIV_LOCH 2, EN_DIV2_DIVPROG 0
[11:44:08] DEBUG: VCO 4800.00 MHz, RefClk 30.72 MHz
[11:44:08] DEBUG: ICT_VCO: 128
[11:44:08] DEBUG: csw=64 cmphl=0
[11:44:08] DEBUG: csw=96 cmphl=0
[11:44:08] DEBUG: csw=112 cmphl=0
[11:44:08] DEBUG: csw=120 cmphl=0
[11:44:08] DEBUG: csw=124 cmphl=0
[11:44:08] DEBUG: csw=126 cmphl=0
[11:44:08] DEBUG: csw=127 cmphl=0
[11:44:08] DEBUG: Failed to lock
[11:44:08] DEBUG: csw=192 cmphl=0
[11:44:08] DEBUG: csw=224 cmphl=3
[11:44:08] DEBUG: csw=208 cmphl=3
[11:44:08] DEBUG: csw=200 cmphl=2
[11:44:08] DEBUG: csw=204 cmphl=3
[11:44:08] DEBUG: csw=202 cmphl=3
[11:44:08] DEBUG: csw=201 cmphl=3
[11:44:08] DEBUG: Failed to lock
[11:44:08] DEBUG: cmphl=2
[11:44:08] DEBUG: VCOL : csw=197 tune ok
[11:44:08] DEBUG: ICT_VCO: 128
[11:44:08] DEBUG: csw=64 cmphl=3
[11:44:08] DEBUG: csw=32 cmphl=3
[11:44:08] DEBUG: csw=16 cmphl=2
[11:44:08] DEBUG: csw=24 cmphl=2
[11:44:08] DEBUG: csw=28 cmphl=2
[11:44:08] DEBUG: csw=30 cmphl=2
[11:44:08] DEBUG: csw=31 cmphl=2
[11:44:08] DEBUG: CSW: lowest=16, highest=31, selected=23
[11:44:08] DEBUG: csw=192 cmphl=3
[11:44:08] DEBUG: csw=160 cmphl=3
[11:44:08] DEBUG: csw=144 cmphl=3
[11:44:08] DEBUG: csw=136 cmphl=3
[11:44:08] DEBUG: csw=132 cmphl=3
[11:44:08] DEBUG: csw=130 cmphl=3
[11:44:08] DEBUG: csw=129 cmphl=3
[11:44:08] DEBUG: Failed to lock
[11:44:08] DEBUG: cmphl=2
[11:44:08] DEBUG: VCOM : csw=23 tune ok
[11:44:08] DEBUG: ICT_VCO: 128
[11:44:08] DEBUG: TuneVCO(SXR) - VCO too high
[11:44:08] DEBUG: VCOH : csw=0 tune fail
[11:44:08] DEBUG: Selected: VCOL
[11:44:08] INFO: SXR frequency set to 600.000000 MHz
[11:44:11] DEBUG: INT 87, FRAC 152917, DIV_LOCH 2, EN_DIV2_DIVPROG 1
[11:44:11] DEBUG: VCO 5600.00 MHz, RefClk 30.72 MHz
[11:44:11] DEBUG: ICT_VCO: 128
[11:44:11] DEBUG: TuneVCO(SXT) - VCO too low
[11:44:11] DEBUG: VCOL : csw=0 tune fail
[11:44:11] DEBUG: ICT_VCO: 128
[11:44:11] DEBUG: csw=64 cmphl=0
[11:44:11] DEBUG: csw=96 cmphl=2
[11:44:11] DEBUG: csw=112 cmphl=3
[11:44:11] DEBUG: csw=104 cmphl=3
[11:44:11] DEBUG: csw=100 cmphl=2
[11:44:11] DEBUG: csw=102 cmphl=3
[11:44:11] DEBUG: csw=101 cmphl=2
[11:44:11] DEBUG: CSW: lowest=96, highest=101, selected=98
[11:44:11] DEBUG: csw=192 cmphl=3
[11:44:11] DEBUG: csw=160 cmphl=3
[11:44:11] DEBUG: csw=144 cmphl=3
[11:44:11] DEBUG: csw=136 cmphl=3
[11:44:11] DEBUG: csw=132 cmphl=3
[11:44:11] DEBUG: csw=130 cmphl=3
[11:44:11] DEBUG: csw=129 cmphl=3
[11:44:11] DEBUG: Failed to lock
[11:44:11] DEBUG: cmphl=2
[11:44:11] DEBUG: VCOM : csw=98 tune ok
[11:44:11] DEBUG: ICT_VCO: 128
[11:44:11] DEBUG: TuneVCO(SXT) - VCO too high
[11:44:11] DEBUG: VCOH : csw=0 tune fail
[11:44:11] DEBUG: Selected: VCOM
[11:44:11] INFO: SXT frequency set to 700.000000 MHz
[11:44:16] DEBUG: MCU algorithm time: 11 ms
[11:44:16] DEBUG: MCU algorithm time: 0 ms
[11:44:16] DEBUG: MCU algorithm time: 0 ms
[11:44:16] DEBUG: MCU algorithm time: 121 ms
[11:44:16] ERROR: Rx calibration: MCU error 5 (Loopback signal weak: not connected/insufficient gain?)
[11:44:18] DEBUG: MCU algorithm time: 0 ms
[11:44:18] DEBUG: MCU algorithm time: 0 ms
[11:44:18] DEBUG: MCU algorithm time: 0 ms
[11:44:18] DEBUG: MCU algorithm time: 105 ms
[11:44:18] ERROR: Tx Calibration: MCU error 5 (Loopback signal weak: not connected/insufficient gain?)
[11:44:21] DEBUG: MCU algorithm time: 0 ms
[11:44:21] DEBUG: MCU algorithm time: 0 ms
[11:44:21] DEBUG: MCU algorithm time: 0 ms
[11:44:21] DEBUG: MCU algorithm time: 121 ms
[11:44:21] ERROR: Rx calibration: MCU error 5 (Loopback signal weak: not connected/insufficient gain?)
[11:44:23] DEBUG: MCU algorithm time: 0 ms
[11:44:23] DEBUG: MCU algorithm time: 0 ms
[11:44:23] DEBUG: MCU algorithm time: 0 ms
[11:44:23] DEBUG: MCU algorithm time: 105 ms
[11:44:23] ERROR: Tx Calibration: MCU error 5 (Loopback signal weak: not connected/insufficient gain?)
Try this config, this is a calibration stage at which your board is failing: https://www.dropbox.com/s/t0za0z6eix3u1gi/TxRxLoopback.ini?dl=0
Same as previously after loading, press calculate in SXR, SXT and CGEN tabs.
Open FFT viewer and you should see something similar to this:
If your highest spike is lower try: in TxTSP tab, enter DC_REG: 7FFF, press both Load to DC I/Q buttons.
Try this config to check if B channel works: https://www.dropbox.com/s/oouob5k1e7j5abe/MIMO_TxTSGNCO_LB.ini?dl=0
Same as previously after loading, press calculate in SXR, SXT and CGEN tabs.
In FFTviewer set data reading to LMS MIMO, and change Display channel to A&B.
Should look similar to this:
Also I’ve used these same tests against my working LimeSDR 1.4 unit and results look similar to yours so I believe I’m doing everything correctly.
Yeah, looks bad. That should have been chip’s internal Tx->Rx loopback, looks like Rx is not getting anything. Most likely some hardware failure, don’t know what could be the reason, it’s out of my expertise.
From brief look at the chip’s block diagrams, here’s config to bypass some of the analog blocks: https://www.dropbox.com/s/6lsrp58j5aut8zc/MIMO_TxTSGNCO_BB_LB.ini?dl=0
You should see something like this:
@ricardas Hmm, finally one that looks similar to yours…What does this mean that this FFT graph looks similar?
Andrew or Zack, Any opinions as to what could be wrong with the hardware? I’m not sure what to do at this point. It’s been quite a long time since I ordered this LimeSDR from Crowd Supply and I never fully tested it’s functionality when I received it since I had my other LimeSDR 1.4 that I was using. Once I got around to testing it, I could never get it to receive signals properly and figured it was something misconfigured on the software side, but now its pretty clear that something is likely wrong with the hardware.
well, that means software, firmware, and chip’s digital parts are working correctly.
Also that indicates the problem is in chip receiver’s analog part.
Maybe it got somehow damaged during board modification, did you tried it before attempting to modify it?
Anyway, this is as much as I could help. I can only guess about hardware issues.
In summary:
Chip’s TBB->RBB loopback works.
Chip’s internal RF loopback shows no signals on both A&B channels.
So I assume the problem should be with SXR block, as it is common for both A&B channels (although calibration did not report errors of not being able to lock PLL)
@ricardas Well, I know that I tested it right after performing the easy fix on the board and as far as I am aware everything was working correctly at that point. I placed it back in its box and its been sitting on my desk for a couple of months since I have another LimeSDR that I’ve been using. After pulling it out and once again updating the firmware to the latest release I started to run into these problems. I don’t think I’ve done anything different with this board compared to any of the others so I’m at a loss as to what caused the damage.
BTW Thank you for all of your assistance Ricardas. I really appreciate all of the time you’ve spent providing information and helping me run through these tests. Its definitely bad news, but at least I have confirmation at this point.
Perhaps a question for @Zack or @andrewback or someone else on the Lime Micro team:
Does Lime Micro offer any sort of repair service? This board was only used a few times when I first got it and it seems like most of the other components are working so I’d hate for this to be an expensive paper weight considering everything. Any assistance on what I can do to get this fixed, if possible, is appreciated.
Thanks again,
Justin