# LimeSDR-USB FPGA register map

**URL:** <https://discourse.myriadrf.org/t/limesdr-usb-fpga-register-map/7327>\
**Category:** LimeSDR\
**Created:** [1 September 2021 02:30 UTC](https://discourse.myriadrf.org/t/limesdr-usb-fpga-register-map/7327 "2021-09-01T02:30:42Z")\
**Posts on this page:** 6\
**Page:** 1

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**Author:** ![TimBat](https://avatars.discourse-cdn.com/v4/letter/t/ea5d25/32.png) [@TimBat](https://discourse.myriadrf.org/u/TimBat)\
**Post date:** [1 September 2021 02:30 UTC](https://discourse.myriadrf.org/t/limesdr-usb-fpga-register-map/7327/1 "2021-09-01T02:30:42Z")

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CC @andrewback

I’m trying to add some custom logic into my LimeSDR-USB and need to access a register.

Reading through the RTL I’ve seen that register 24 is spare, and I have successfully used LMS\_ReadFPGAReg and LMS\_WriteFPGAReg to verify R/W operation here.

My question, is there a register map in documentation where this is laid out ?

Is there a more general access method for accessing any register (in LMS7002M, FPGA, FX3 etc).

Is there any support for self clearing registers ? What about clock domains for the registers ?

Thanks Tim

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**Author:** ![andrewback](https://avatars.discourse-cdn.com/v4/letter/a/22d042/32.png) [@andrewback](https://discourse.myriadrf.org/u/andrewback)\
**Post date:** [1 September 2021 04:41 UTC](https://discourse.myriadrf.org/t/limesdr-usb-fpga-register-map/7327/2 "2021-09-01T04:41:12Z")

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@Zack Perhaps you could advise.

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [2 September 2021 05:17 UTC](https://discourse.myriadrf.org/t/limesdr-usb-fpga-register-map/7327/3 "2021-09-02T05:17:15Z")

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Hi @TimBat

Check FPGA gateware description for more information:

> **[LimeSDR-USB\_GW/doc at master · myriadrf/LimeSDR-USB\_GW](https://github.com/myriadrf/LimeSDR-USB_GW/tree/master/doc)**
>
> master/doc

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**Author:** ![TimBat](https://avatars.discourse-cdn.com/v4/letter/t/ea5d25/32.png) [@TimBat](https://discourse.myriadrf.org/u/TimBat)\
**Post date:** [2 September 2021 05:43 UTC](https://discourse.myriadrf.org/t/limesdr-usb-fpga-register-map/7327/4 "2021-09-02T05:43:26Z")

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Great help thanks!

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**Author:** ![TimBat](https://avatars.discourse-cdn.com/v4/letter/t/ea5d25/32.png) [@TimBat](https://discourse.myriadrf.org/u/TimBat)\
**Post date:** [8 September 2021 02:40 UTC](https://discourse.myriadrf.org/t/limesdr-usb-fpga-register-map/7327/5 "2021-09-08T02:40:36Z")

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@Zack I have added a 1PPS into GPIO header, and I can read the register and see the pulse at times when lucky enough to poll it.

I’m wanting to add a hex string into the stream when 1PPS fires with a register based trigger, where would you suggest is the best place to insert such functionality into the FPGA ? I’m VHDL fluent

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**Author:** ![andrin](https://avatars.discourse-cdn.com/v4/letter/a/8e7dd6/32.png) [@andrin](https://discourse.myriadrf.org/u/andrin)\
**Post date:** [25 October 2021 05:58 UTC](https://discourse.myriadrf.org/t/limesdr-usb-fpga-register-map/7327/6 "2021-10-25T05:58:47Z")

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Hi Tim

A bit hacky:  
You could hitchhike the PPS info into the packet header.

The first two documented bits (see packet structure, bits 3 and 4) are basically only TX relevant, and therefore unused for RX packets.

The downside is that thus is only streamed back at payload granularity. But with a PPS, there is plenty of room to serialize quite some information on the relative timing of pps wrt to sample count.