LimeSDR Signal Generator

This .ini should give you sine wave at 750MHz from TX_1_2 output. Just botched the config, can’t guarantee anything, as I don’t have tools to check it right now. Further gain and calibration adjustments should be done.

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Thanks @ricardas … This is really very helpful! :slight_smile:

Programmed the Arduino Due to make the LimeSDR do a bit of frequency hopping at 20ms:

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Very cool. Any chance we could see some code?

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@ricardas,
The SXT frequency is set to 730. I can’t find where the other 20MHz comes from. It may be instructive to find out what you did.

Second to that… I need some code like that in RPI2 or 3 B :wink:

@gerryk @9a4db Here’s a bit more info on the set up:

The crux of the code is here:

LMS7002M_WR(0x011D, 0xEAAA);
delay (20);
LMS7002M_WR(0x011D, 0xEABA);
delay (20);
LMS7002M_WR(0x011D, 0xEACA);
delay (20);
LMS7002M_WR(0x011D, 0xEADA);
delay (20);
LMS7002M_WR(0x011D, 0xEAEA);

// Write register value to LMS7002M via SPI
void LMS7002M_WR(int addr, int val)
{
digitalWrite(LMS7_SS_Pin, LOW);
SPI.transfer( ((addr >> 8) | 0x80) );
SPI.transfer( (addr & 0xFF) );
SPI.transfer( ((val >> 8) & 0xFF) );
SPI.transfer( (val & 0xFF) );
digitalWrite(LMS7_SS_Pin, HIGH);
}

And here’s the hardware set up:


To use the Arduino Due the little orange PCB is required to convert 0.05" pitch JTAG connectors to 0.1" pitch for ease of use. Trying to botch this up is not recommended! There’s also special code to upload to the FPGA for enabling external SPI, which is very straight forwards:

https://cdn.hackaday.io/files/20500877072000/Arduino_2_LimeSDR-USB_HW_1.4.rbf

… and to put it back to normal use:

https://cdn.hackaday.io/files/20500877072000/LimeSDR-USB_lms7_trx_HW_1.4.rbf

The full Arduino code is here:

https://cdn.hackaday.io/files/20500877072000/Signal_generator_01.ino

PS. The SPI is 3v and is only compatible with the Due unless level shifters or resistors are used.

Yes it would be very interesting to know where the 20 MHz disappears to! It does work though.

Excellent thanks. I find code so much easier to understand than documentation.

Single ‘Tone’:
com-video-to-gif (1)

It should be easy to configure some GPIO pins as SPI and reuse the code posted. Otherwise just use pyLMS7002 or SoapySDR.

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There are multiple ways to achieve the same effect.

In my case, Tx carrier wave is set to 730MHz and TxTSP is set to generate test signal(sine wave) at 1/4th Tx sampling rate, which is (160MHz CGEN)/(2 IQ channels)/4=20MHz
tsg

Doing frequency hopping this way is not correct, as this could only work for extremely small changes. If you change (0x011D or 0x011E) too much, PLL can lose lock and would need retuning.

To change center frequency reliably you need to write correct values to these registers:
0x011C[10], 0x011D, 0x011E, 0x011F[8:6], 0x0121[10:1]

Or use NCO to upconvert/downconvert your signal. It’s possible to have 16 frequency offests configured in 0x0241:0x0261 registers, and switch between them using 0x0240[4:1] bits.

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Thanks @ricardas, that make sense.

There must be a formula to tune the frequency using the above registers?
So, if:

a=0x011C[10],
b=0x011D,
c=0x011E,
d=0x011F[8:6],
e =0x0121[10:1]
and f is the desired frequency,

What’s the mathematical relationship between a,b,c,d,e and f?

If we used lime as signal generator whats the lowest and highest frequency we can used it for and what kind signal we can used like “square,triangle,noise etc”

If you like Python then the examples at

look like a good place to start.

Yes I expect that the information is in there somewhere but rather like looking for a needle in a haystack. Somebody at lime Microsystems should know what the formula is without too much bother. Maybe @andrewback might know who the best person to ask is?

Here’s the procedure used to set all those registers SetFrequencySX , you should see the relationships there.
only the 0x0121[10:1] can’t be calculated exactly, so it needs to be searched dynamically using this procedure TuneVCO

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@ricardas
Thank you for the post.
i am trying to open on limesuite using “TxSine750M.ini” given in the post on Ubuntu 18.04 but unfortunately i’m having the following errors that i have attached. my platform is VMWare running ubuntu 18.04 with host operating system as windows 10.

can you help me out please?

In CLKGEN tab, change CLKH_OV_CLKL to 4