# LimeSDR RXOUT and clock sync

**URL:** <https://discourse.myriadrf.org/t/limesdr-rxout-and-clock-sync/2072>\
**Category:** LimeSDR\
**Created:** [29 November 2017 09:16 UTC](https://discourse.myriadrf.org/t/limesdr-rxout-and-clock-sync/2072 "2017-11-29T09:16:15Z")\
**Posts on this page:** 1\
**Showing post:** 3

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**Author:** ![acube](https://avatars.discourse-cdn.com/v4/letter/a/eb8c5e/32.png) [@acube](https://discourse.myriadrf.org/u/acube)\
**Post date:** [29 November 2017 10:51 UTC](https://discourse.myriadrf.org/t/limesdr-rxout-and-clock-sync/2072/3 "2017-11-29T10:51:34Z")

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Hi @Zack,  
Thanks a lot for your quick reply !

> [@Zack](#):
>
> I do not know your application, but LMS7002M is 2x2 MIMO. Maybe one board is enough?

You’re right, for the beginning, one LimeSDR board could be enough to measure if there’s a phase-shift between the two receivers. It really depends on the sampling frequency of the IQ signals. The idea is to be as precise as possible to detect nanoseconds of phase-shift.

Assuming I will use the LimeSDR for my project:

1. Will it be possible to get the I/Q signals on the GPIOs (or some external pins) ?
2. If yes, what will be the sampling rate of the I/Q signals at that stage ?

Regarding the last question: I read in another post ([here](https://discourse.myriadrf.org/t/generate-chirp-signal-using-lime-sdr/1690/13)) one of your reply saying that the ADC works at 80MHz :

> “You have 4 ADCs running at 80MHz in parallel; this is 4 Samples \* 80 MHz = 320 MSps (mega samples per second);”

- If I get it correctly, that means the I and Q signals will be sampled at 80MHz by the IQADC. Is that correct ?
- Cause in the LMS7002M datasheet, I read that the ADCs are running at 160MHz, am I missing something ?
- Is there a way to increase the sampling rate ?
- After the IQADC, is there any other re-sampling of the IQ signals ?

Thanks a lot for your help.  
David

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