# LimeSDR PCIe: RIFFA 2.2 vs Xillybus (open source vs license)

**URL:** <https://discourse.myriadrf.org/t/limesdr-pcie-riffa-2-2-vs-xillybus-open-source-vs-license/3194>\
**Category:** LimeSDR\
**Created:** [20 August 2018 16:59 UTC](https://discourse.myriadrf.org/t/limesdr-pcie-riffa-2-2-vs-xillybus-open-source-vs-license/3194 "2018-08-20T16:59:46Z")\
**Posts on this page:** 1\
**Page:** 1

<div class="post-metadata">

**Author:** ![robalenper](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/robalenper/32/613_2.png) [@robalenper](https://discourse.myriadrf.org/u/robalenper)\
**Post date:** [20 August 2018 16:59 UTC](https://discourse.myriadrf.org/t/limesdr-pcie-riffa-2-2-vs-xillybus-open-source-vs-license/3194/1 "2018-08-20T16:59:46Z")

</div>

I’ve learned that there is an open source PCIe IP called RIFFA 2.2

@andrewback @Zack

Is there a plan to upgrade the LimeSDR PCIe with a FPGA which has a Gen2 transceiver (Cyclone IV GX is Gen1)? Maybe for the next Lime Transceiver generation?

And maybe the LimeSDR PCIe board can have a reduced price if the Xillybus license fee is removed and instead the RIFFA 2.2 PCIe IP is used?

- Xillybus has an upper limit of 400 MB/s in PCIe x4.
- RIFFA 2.2 claims a much higher limit due to the novel architecture
  - In Cyclone V, I got these numbers from someone who is experimenting with this IP:  
“ **_I was seeing 209Mb/s for gen1\_x1 and 411Mb/s for gen2\_x1 settings._** ”
  - If this is reproducible in Cyclone IV, we would get 800Mbps (6.4Gbps), it is double the performance of Xillybus.

If LimeSDR PCIe is scheduled for an upgrade in the future, then a small Cyclone V GT with 5.0Gbps transceivers would give 18Gbps in Gen2 4x with Open Source RIFFA PCIe IP!!

References:

RIFFA 2.2

> **[riffa\_documentation.pdf](https://github.com/KastnerRG/riffa/blob/master/docs/riffa_documentation.pdf)**

> **[trets15-riffa21.pdf](https://kastner.ucsd.edu/wp-content/uploads/2013/08/admin/trets15-riffa21.pdf)**
>
> 1431.00 KB

> **[GitHub - KastnerRG/riffa: The RIFFA development repository](https://github.com/KastnerRG/riffa)**
>
> The RIFFA development repository

Cyclone IV Gen1 limit:

> **[cyiv-52001.pdf](https://cdrdv2-public.intel.com/655160/cyiv-52001.pdf)**

 ![image](https://yyz2.discourse-cdn.com/flex034/uploads/myriadrf/original/2X/a/af58cffe6b3857d2ae6739d65659d5d2c745f7b3.png)

Xillybus 400 MB/s upper limit:

> **[Xillybus' data bandwidth | xillybus.com](https://xillybus.com/doc/xillybus-bandwidth)**

Reference discussion from @Zack

> [@Max Bandwidth of Dual RX](https://discourse.myriadrf.org/t/max-bandwidth-of-dual-rx/307/7):
>
> I assume you are interesting in RX data only. Then there are a few things to consider: Maximum USB3 data throughput from LimeSDR-USB to PC. Maximum theoretical data throughput in this case is 400MB/s (32 bit interface between USB MCU (FX3) and FPGA running @ 100MHz). Real number we were to achieve with LimeSDR-USB is 387MB/s. Maximum RF bandwidth of LMS7002M analog frontend. Theoretically it is limited by ADC sample rate (while filters in the analogue frontend may be bypassed) which is 160MHz.…