The LimeSDR-mini only has 549 Kb of RAM in the FPGA whereas the LimeSDR-USB has 256MiB of DDR2 SDRAM which is roughly 4000x the space that could be used for buffering as well as 1134 Kbits of RAM in its FPGA.
I think that there may also be more efficient bit-packing in terms of USB bandwidth but less efficient in that it generates more heat that must be dissipated used by the LimeSDR-USB. And so to reduce the cooling requirements for a much smaller board I think that a simpler bit-packing was used, but I still need to fully read through the gateware doodling patterns of bits with a pencil and paper to verify. But speed reading it I think that the mini packs four 12-bit samples (or two pairs of 12-bit IQ samples) into each 64-bit word, for transfers across the USB bus. This would also reduces the processing overhead of multi-word bit manipulation on the PC before samples can actually be used for anything, so it has upsides. Also since the LimeSDR-mini was designed to have a maximum sample rate of 30.72 MSPS and does not need to support MIMO, it should not need to go to such extremes of tight bit-packing to transfer enough samples across the USB bus. There is also the possibility that there may not even be enough free Logic Elements in the mini’s FPGA to implement the more complex bit-packing anyhow, irregardless of the extra cooling requirements.