# LimeSDR Micro/M.2/XTRX: Match validation of 700MHz-2.6GHz RX port?

**URL:** <https://discourse.myriadrf.org/t/limesdr-micro-m-2-xtrx-match-validation-of-700mhz-2-6ghz-rx-port/13292>\
**Category:** Uncategorized\
**Created:** [10 August 2026 14:39 UTC](https://discourse.myriadrf.org/t/limesdr-micro-m-2-xtrx-match-validation-of-700mhz-2-6ghz-rx-port/13292 "2026-08-10T14:39:26Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![ajalali](https://avatars.discourse-cdn.com/v4/letter/a/65b543/32.png) [@ajalali](https://discourse.myriadrf.org/u/ajalali)\
**Post date:** [10 August 2026 14:39 UTC](https://discourse.myriadrf.org/t/limesdr-micro-m-2-xtrx-match-validation-of-700mhz-2-6ghz-rx-port/13292/1 "2026-08-10T14:39:26Z")

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Hi all,

I’m working on a custom board design around the LMS7002M. Our freq band aligns with the upper portion of the wideband match on some of the LimeSDR boards, shown here. But I’m struggling to replicate the match in simulation using vendor models. I’m curious if anyone else is using this port and has done return loss/matching validation in hardware?

**Schematic snippet**

 ![image](https://canada1.discourse-cdn.com/flex034/uploads/myriadrf/original/2X/8/80068368ec2e36cfc795f7bde54ba036a3683baa.png)

**My attempt at simulating in Genesys**

 ![image](https://canada1.discourse-cdn.com/flex034/uploads/myriadrf/original/2X/3/3c2d84b668f97cdd3b66973f15a6dc0033361634.png)

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**Author:** ![andrewback](https://avatars.discourse-cdn.com/v4/letter/a/22d042/32.png) [@andrewback](https://discourse.myriadrf.org/u/andrewback)\
**Post date:** [13 August 2026 08:14 UTC](https://discourse.myriadrf.org/t/limesdr-micro-m-2-xtrx-match-validation-of-700mhz-2-6ghz-rx-port/13292/2 "2026-08-13T08:14:56Z")

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Tagging @Karolis