# LimeSDR FPGA upgrade to EP4CE115F23C8 (?)

**URL:** <https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010>\
**Category:** LimeSDR\
**Created:** [25 March 2017 20:27 UTC](https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010 "2017-03-25T20:27:27Z")\
**Posts on this page:** 1\
**Showing post:** 9

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**Author:** ![robalenper](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/robalenper/32/613_2.png) [@robalenper](https://discourse.myriadrf.org/u/robalenper)\
**Post date:** [26 March 2017 08:56 UTC](https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010/9 "2017-03-26T08:56:19Z")

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Just an update, I was able to synthesize the “original/unmodified” design successfully.

I had an initial issue because I was running with a newer Quartus version. The issue was resolved when running with version 15.1.

 ![](https://canada1.discourse-cdn.com/flex034/uploads/myriadrf/original/1X/024ae8a03faaa10769b77786767b6167cd9dee89.png)

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_[View the full topic](https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010)._