# LimeSDR FPGA upgrade to EP4CE115F23C8 (?)

**URL:** <https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010>\
**Category:** LimeSDR\
**Created:** [25 March 2017 20:27 UTC](https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010 "2017-03-25T20:27:27Z")\
**Posts on this page:** 9\
**Page:** 1

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**Author:** ![robalenper](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/robalenper/32/613_2.png) [@robalenper](https://discourse.myriadrf.org/u/robalenper)\
**Post date:** [25 March 2017 20:27 UTC](https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010/1 "2017-03-25T20:27:27Z")

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Hi All,

As I noticed that the Blade RF SDR board has the option of using either the 40K ( EP4CE40F23C8) or 115K ( EP4CE115F23C8) Altera device, I would like to check if LimeSDR could be upgraded to the device EP4CE115F23C8 using hot air BGA reflowing?

I tried checking if EP4CE115F23 would need changes in the pin assignments but it seems that the top level entity is missing in the github repo, so I’m not sure if we can rebuild the FPGA project.

Has anyone investigated this and rebuilt the FPGA from github files successfully?

In the Altera setting file: [https://github.com/myriadrf/LimeSDR-USB\_GW/blob/master/LimeSDR-USB\_lms7\_trx.qsf](https://github.com/myriadrf/LimeSDR-USB_GW/blob/master/LimeSDR-USB_lms7_trx.qsf)

The top level and device information is:  
set\_global\_assignment -name FAMILY “Cyclone IV E”  
set\_global\_assignment -name DEVICE EP4CE40F23C8  
set\_global\_assignment -name TOP\_LEVEL\_ENTITY lms7\_trx\_top  
set\_global\_assignment -name ORIGINAL\_QUARTUS\_VERSION 15.0.0

But I could not find the entity “lms7\_trx\_top” in the source files.

Could anyone check if github has all the RTL files to rebuild the FPGA?

Once I’m able to rebuild, I would like to check what is needed to port the Altera project to DEVICE EP4CE115F23C8.

Thanks, Rob KK6IOZ

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**Author:** ![Kryan92](https://avatars.discourse-cdn.com/v4/letter/k/e480ec/32.png) [@Kryan92](https://discourse.myriadrf.org/u/Kryan92)\
**Post date:** [26 March 2017 04:01 UTC](https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010/2 "2017-03-26T04:01:08Z")

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The EP4CE115F23C8 has less I/O available to it than the 40k chip, so certain pins aren’t available to be used. Without checking what ones these were, I changed the compilation settings for the default gateware to that device and tried it.

I got the following errors during synthesis:  
Error (171016): Can’t place node “FPGA\_GPIO0” – illegal location assignment PIN\_H8  
Error (171016): Can’t place node “FPGA\_GPIO4” – illegal location assignment PIN\_G4  
Error (171016): Can’t place node “FX3\_CTL7” – illegal location assignment PIN\_M7  
Error (171016): Can’t place node “FX3\_CTL1” – illegal location assignment PIN\_L7  
Error (171016): Can’t place node “FPGA\_SPI1\_SCLK” – illegal location assignment PIN\_K8  
Error (171016): Can’t place node “FPGA\_SPI1\_MOSI” – illegal location assignment PIN\_L8  
Error (171016): Can’t place node “FPGA\_SPI1\_ADF\_SS” – illegal location assignment PIN\_J5  
Error (171016): Can’t place node “FX3\_DQ[31]” – illegal location assignment PIN\_N16  
Error (171016): Can’t place node “FX3\_DQ[30]” – illegal location assignment PIN\_N17  
Error (171016): Can’t place node “FX3\_DQ[24]” – illegal location assignment PIN\_P15  
Error (171016): Can’t place node “FX3\_DQ[23]” – illegal location assignment PIN\_P16  
Error (171016): Can’t place node “FX3\_DQ[19]” – illegal location assignment PIN\_R18  
Error (171016): Can’t place node “FX3\_DQ[12]” – illegal location assignment PIN\_U19  
Error (171016): Can’t place node “FX3\_DQ[3]” – illegal location assignment PIN\_Y21  
Error (171016): Can’t place node “BRDG\_SPI\_FPGA\_SS” – illegal location assignment PIN\_K7  
Error (171016): Can’t place node “FX3\_CTL8” – illegal location assignment PIN\_M8  
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00  
Error (171000): Can’t fit design in device  
Error: Quartus Prime Fitter was unsuccessful. 17 errors, 4 warnings  
Error: Peak virtual memory: 924 megabytes  
Error: Processing ended: Sat Mar 25 23:57:21 2017  
Error: Elapsed time: 00:00:12  
Error: Total CPU time (on all processors): 00:00:10  
Error (293001): Quartus Prime Full Compilation was unsuccessful. 19 errors, 82 warnings

Without going into what pins aren’t and are available, it seems at least these aren’t physically available on that package.

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**Author:** ![robalenper](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/robalenper/32/613_2.png) [@robalenper](https://discourse.myriadrf.org/u/robalenper)\
**Post date:** [26 March 2017 04:15 UTC](https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010/3 "2017-03-26T04:15:01Z")

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The EP4CE115F23 has only 4 user I/O pins less than EP4CE30/40 (528 vs 532), maybe a careful pin remapping for the 16 assignment errors would solve the problem (maybe also RTL change), but we would need to check the schematics and how the pin reassignments would work. I’m guessing that a similar approach may have been done in Blade RF 40x and x115.

I haven’t tried to rebuild the FPGA, let me try as well but we may need some support and guidance from the LimeSDR digital designers.

> **[cyiv-51001.pdf](https://cdrdv2-public.intel.com/654630/cyiv-51001.pdf)**

 ![](https://canada1.discourse-cdn.com/flex034/uploads/myriadrf/original/1X/6de655844037f8186d555328277ff1e3156abb46.png)

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**Author:** ![Kryan92](https://avatars.discourse-cdn.com/v4/letter/k/e480ec/32.png) [@Kryan92](https://discourse.myriadrf.org/u/Kryan92)\
**Post date:** [26 March 2017 04:18 UTC](https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010/4 "2017-03-26T04:18:12Z")

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Wrong package. The chip on-board is F484. There are a max of 328 I/O to 280 I/O.

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**Author:** ![robalenper](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/robalenper/32/613_2.png) [@robalenper](https://discourse.myriadrf.org/u/robalenper)\
**Post date:** [26 March 2017 04:37 UTC](https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010/5 "2017-03-26T04:37:52Z")

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Thanks for the correction on the package.

Not a trivial remapping in fact. Maybe if we check how this was done in the Blade RF, we can get some hints.

Do you know if LimeSDR designers can get involved to provide some guidance for this experiment to comment whether it is doable with RTL/pin assignment changes or only possible with a board/design change?

 ![](https://canada1.discourse-cdn.com/flex034/uploads/myriadrf/original/1X/b2c54d0c1b04502aff81e89a95707c8cbde2b917.png)

 ![](https://canada1.discourse-cdn.com/flex034/uploads/myriadrf/original/1X/6def3f098b357ff3eaf207856e056d46be16e6fb.png)

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<div class="post-metadata">

**Author:** ![Kryan92](https://avatars.discourse-cdn.com/v4/letter/k/e480ec/32.png) [@Kryan92](https://discourse.myriadrf.org/u/Kryan92)\
**Post date:** [26 March 2017 04:56 UTC](https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010/6 "2017-03-26T04:56:35Z")

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The BladeRF designers had to have the 115k in mind when they designed their board, so as to not use any pins that aren’t completely shared between the 40k and 115k packages. In this case it seems critical I/O on the 40k package (FX3 databus and SPI lines) are mapped to pins that aren’t available on the 115k variant.

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**Author:** ![robalenper](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/robalenper/32/613_2.png) [@robalenper](https://discourse.myriadrf.org/u/robalenper)\
**Post date:** [26 March 2017 07:50 UTC](https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010/7 "2017-03-26T07:50:55Z")

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I’m not a FPGA expert but in the Quartus “Pin Planner”, there is a “Pin Migration Window”.

When I selected a migration for the project, the device EP4CE115F23C8 was considered a compatible migration. Then I noticed that the pins which caused errors in your compilation were either VCCINT or GND as below.

It looks like there might be a way and someone with expertise in Altera projects would recommend a migration plan. I will also check with some coworkers who might have expertise in this area of FPGA migration.

 ![](https://canada1.discourse-cdn.com/flex034/uploads/myriadrf/original/1X/7ebf84009b8a2bb305ce6d5ee1f09d8e207eeded.png)

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<div class="post-metadata">

**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [26 March 2017 08:22 UTC](https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010/8 "2017-03-26T08:22:51Z")

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> [@FPGA package migration?](https://discourse.myriadrf.org/t/fpga-package-migration/606):
>
> Is the current EP4CE40F23C8 using the F484 package? Does that mean it would be possible to mount a EP4CE115 on the LimeSDR?

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**Author:** ![robalenper](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/robalenper/32/613_2.png) [@robalenper](https://discourse.myriadrf.org/u/robalenper)\
**Post date:** [26 March 2017 08:56 UTC](https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010/9 "2017-03-26T08:56:19Z")

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Just an update, I was able to synthesize the “original/unmodified” design successfully.

I had an initial issue because I was running with a newer Quartus version. The issue was resolved when running with version 15.1.

 ![](https://canada1.discourse-cdn.com/flex034/uploads/myriadrf/original/1X/024ae8a03faaa10769b77786767b6167cd9dee89.png)