# LimeSDR FPGA programming Quartus Project

**URL:** <https://discourse.myriadrf.org/t/limesdr-fpga-programming-quartus-project/6960>\
**Category:** LimeSDR\
**Created:** [15 February 2021 09:23 UTC](https://discourse.myriadrf.org/t/limesdr-fpga-programming-quartus-project/6960 "2021-02-15T09:23:57Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![nachol2013](https://avatars.discourse-cdn.com/v4/letter/n/71e660/32.png) [@nachol2013](https://discourse.myriadrf.org/u/nachol2013)\
**Post date:** [15 February 2021 09:23 UTC](https://discourse.myriadrf.org/t/limesdr-fpga-programming-quartus-project/6960/1 "2021-02-15T09:23:57Z")

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Hello!

I bought in September a Lime SDR in order to implement some projects I had in mind. Up to now, I have been using Lime SDR with Lime Suite or MATLAB. However, now, I want to be able to use the SDR without my computer and I do not know if this is possible. I was thinking about modifying the Quartus project in order to program the signal processing I am intending to do into the FPGA logics. Has anyone tried this? Is there a simpler way to use the SDR without a computer?  
If editting the Qaurtus project is the way to go, I am having issues finding the RX bitstream in the Quartus project. I got all the FPGA code from [https://github.com/myriadrf/LimeSDR-USB\_GW](https://github.com/myriadrf/LimeSDR-USB_GW) Can anyone show me what I may be doing wrong?

I am very grateful for all your help:)

Nacho

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [23 February 2021 11:06 UTC](https://discourse.myriadrf.org/t/limesdr-fpga-programming-quartus-project/6960/2 "2021-02-23T11:06:54Z")

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Hi @nachol2013,

> [@nachol2013](#):
>
> I am having issues finding the RX bitstream in the Quartus project.

Not sure what do you mean, but there are various flavors of compiled bitstreams:

> **[LimeSDR-USB\_GW/output\_files at master · myriadrf/LimeSDR-USB\_GW](https://github.com/myriadrf/LimeSDR-USB_GW/tree/master/output_files)**
>
> Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board - myriadrf/LimeSDR-USB\_GW

Gateware description may be useful for you as well:

> **[LimeSDR-USB\_GW/doc at master · myriadrf/LimeSDR-USB\_GW](https://github.com/myriadrf/LimeSDR-USB_GW/tree/master/doc)**
>
> Altera Cyclone IV FPGA project for the USB 3.0 LimeSDR board - myriadrf/LimeSDR-USB\_GW