# LimeSDR: DSP implemented in the FPGA

**URL:** <https://discourse.myriadrf.org/t/limesdr-dsp-implemented-in-the-fpga/1790>\
**Category:** LimeSDR\
**Created:** [5 October 2017 14:52 UTC](https://discourse.myriadrf.org/t/limesdr-dsp-implemented-in-the-fpga/1790 "2017-10-05T14:52:52Z")\
**Posts on this page:** 1\
**Showing post:** 11

<div class="post-metadata">

**Author:** ![mzs](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/mzs/32/2678_2.png) [@mzs](https://discourse.myriadrf.org/u/mzs)\
**Post date:** [7 May 2021 17:28 UTC](https://discourse.myriadrf.org/t/limesdr-dsp-implemented-in-the-fpga/1790/11 "2021-05-07T17:28:32Z")

</div>

The information you seek has been in the git repositories for a long time. Take note of the Quartus Prime Version “Lite Edition” used for each if you are going to modify the gateware.

[LimeSDR-USB\_GW](https://github.com/myriadrf/LimeSDR-USB_GW/blob/master/output_files/LimeSDR-USB_lms7_trx.fit.rpt):

```
+----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+---------------------------------------------+
; Fitter Status ; Successful - Thu May 21 11:28:46 2020 ;
; Quartus Prime Version ; 15.1.2 Build 193 02/01/2016 SJ Lite Edition ;
; Revision Name ; LimeSDR-USB_lms7_trx ;
; Top-level Entity Name ; lms7_trx_top ;
; Family ; Cyclone IV E ;
; Device ; EP4CE40F23C8 ;
; Timing Models ; Final ;
; Total logic elements ; 29,220 / 39,600 ( 74 % ) ;
; Total combinational functions ; 23,118 / 39,600 ( 58 % ) ;
; Dedicated logic registers ; 19,666 / 39,600 ( 50 % ) ;
; Total registers ; 19981 ;
; Total pins ; 224 / 329 ( 68 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 832,160 / 1,161,216 ( 72 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 232 ( 0 % ) ;
; Total PLLs ; 4 / 4 ( 100 % ) ;
+------------------------------------+---------------------------------------------+

```

[LimeSDR-Mini\_GW](https://github.com/myriadrf/LimeSDR-Mini_GW/blob/master/LimeSDR-Mini_lms7_trx/output_files/LimeSDR-Mini_lms7_trx.fit.rpt):

```
+----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+---------------------------------------------+
; Fitter Status ; Successful - Tue May 07 14:11:04 2019 ;
; Quartus Prime Version ; 15.1.2 Build 193 02/01/2016 SJ Lite Edition ;
; Revision Name ; LimeSDR-Mini_lms7_trx ;
; Top-level Entity Name ; lms7_trx_top ;
; Family ; MAX 10 ;
; Device ; 10M16SAU169C8G ;
; Timing Models ; Final ;
; Total logic elements ; 14,728 / 15,840 ( 93 % ) ;
; Total combinational functions ; 10,436 / 15,840 ( 66 % ) ;
; Dedicated logic registers ; 11,463 / 15,840 ( 72 % ) ;
; Total registers ; 11561 ;
; Total pins ; 117 / 130 ( 90 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 477,328 / 562,176 ( 85 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 90 ( 0 % ) ;
; Total PLLs ; 1 / 1 ( 100 % ) ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
; ADC blocks ; 0 / 1 ( 0 % ) ;
+------------------------------------+---------------------------------------------+

```

[LimeNET-Micro\_GW](https://github.com/myriadrf/LimeNET-Micro_GW/blob/FTDI/LimeNET-Micro_lms7_trx/output_files/LimeNET-Micro_lms7_trx.fit.rpt):

```
+----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+---------------------------------------------+
; Fitter Status ; Successful - Tue Sep 10 12:04:34 2019 ;
; Quartus Prime Version ; 18.0.0 Build 614 04/24/2018 SJ Lite Edition ;
; Revision Name ; LimeNET-Micro_lms7_trx ;
; Top-level Entity Name ; lms7_trx_top ;
; Family ; MAX 10 ;
; Device ; 10M16SAU169C8G ;
; Timing Models ; Final ;
; Total logic elements ; 15,454 / 15,840 ( 98 % ) ;
; Total combinational functions ; 11,459 / 15,840 ( 72 % ) ;
; Dedicated logic registers ; 11,968 / 15,840 ( 76 % ) ;
; Total registers ; 11998 ;
; Total pins ; 123 / 130 ( 95 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 477,328 / 562,176 ( 85 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 90 ( 0 % ) ;
; Total PLLs ; 1 / 1 ( 100 % ) ;
; UFM blocks ; 1 / 1 ( 100 % ) ;
; ADC blocks ; 0 / 1 ( 0 % ) ;
+------------------------------------+---------------------------------------------+

```

Be warned though that the numbers above are only a snapshot in time (right now), they will fluctuate when updates are made, which have happened.

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_[View the full topic](https://discourse.myriadrf.org/t/limesdr-dsp-implemented-in-the-fpga/1790)._