# Lime PCIE gateway project don't meet time requirements

**URL:** <https://discourse.myriadrf.org/t/lime-pcie-gateway-project-dont-meet-time-requirements/4191>\
**Category:** Reference Development Kit\
**Created:** [14 February 2019 19:52 UTC](https://discourse.myriadrf.org/t/lime-pcie-gateway-project-dont-meet-time-requirements/4191 "2019-02-14T19:52:29Z")\
**Posts on this page:** 2\
**Page:** 1

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**Author:** ![ti\_telecom](https://avatars.discourse-cdn.com/v4/letter/t/ccd318/32.png) [@ti\_telecom](https://discourse.myriadrf.org/u/ti_telecom)\
**Post date:** [14 February 2019 19:52 UTC](https://discourse.myriadrf.org/t/lime-pcie-gateway-project-dont-meet-time-requirements/4191/1 "2019-02-14T19:52:29Z")

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Hi,

I am synthesizing the gateway project to LimePCIe in Quartus II 15.1, but the time requirements are not meet. Does anyone have the same problem?  
How could I proceed in this situation?

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**Author:** ![gasparka](https://avatars.discourse-cdn.com/v4/letter/g/a3d4f5/32.png) [@gasparka](https://discourse.myriadrf.org/u/gasparka)\
**Post date:** [14 February 2019 19:56 UTC](https://discourse.myriadrf.org/t/lime-pcie-gateway-project-dont-meet-time-requirements/4191/2 "2019-02-14T19:56:54Z")

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I have never seen a Quartus project that passes the timing requirements, tho my exposure may not be that great. Anyhow, i would not worry about it.