# How to do HF decimation on FPGA instead of host computer

**URL:** <https://discourse.myriadrf.org/t/how-to-do-hf-decimation-on-fpga-instead-of-host-computer/6953>\
**Category:** System Development\
**Created:** [13 February 2021 01:34 UTC](https://discourse.myriadrf.org/t/how-to-do-hf-decimation-on-fpga-instead-of-host-computer/6953 "2021-02-13T01:34:55Z")\
**Posts on this page:** 1\
**Showing post:** 7

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**Author:** ![mzs](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/mzs/32/2678_2.png) [@mzs](https://discourse.myriadrf.org/u/mzs)\
**Post date:** [13 February 2021 20:52 UTC](https://discourse.myriadrf.org/t/how-to-do-hf-decimation-on-fpga-instead-of-host-computer/6953/7 "2021-02-13T20:52:31Z")

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My guess would be Nyquist limit, so maybe increase the sample rate ? It can go [quite high](https://wiki.myriadrf.org/LimeMicro:LMS7002M_Datasheet#ADCs_electrical_specification). You will need to decimate it afterwards within the TSP to be less than the ~60MHz of bandwidth possible from the digital interface out from the TSP. Maybe even shift your centre frequency higher (or not) for a higher sample rate. The more you decimate the higher the dynamic range, but you will probably need to add an external lowpass/bandpass filter to limit unwanted signals (e.g. Look at the filters on the LimeRFE board).

I’ll point you to this [thread where I learned about the NCO](https://discourse.myriadrf.org/t/problems-with-adapting-the-ask-example-to-15-mhz/4383/6) and decimation. Which is not that long ago actually.

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