If you look at a some of the Opencores for Verilog FFT’s:
64 point fft/ifft - Overview :: Pipelined FFT/IFFT 64 points processor :: OpenCores
- FFT unit for 10 bit data and coefficients, and 2 data buffers occupies 1513 CLB slices, 4 DSP48 blocks, and 2,5 kbit of RAM in Xilinx XC4SX25 FPGA, and 700 CLB slices 4 DSP48E blocks, and 2,5 kbit of RAM in Xilinx XC5SX25 FPGA, data buffers are implemented on the distributed RAM.
128 point fft/ifft - Overview :: Pipelined FFT/IFFT 128 points processor :: OpenCores
- FFT unit for 10 bit data and coefficients, and 3 data buffers occupies 4147 CLB slices, 4 DSP48 blocks, and 5 kbit of RAM in Xilinx XC4SX35 FPGA, and 1254 CLB slices 4 DSP48E blocks, and 5 kbit of RAM in Xilinx XC5VLX30 FPGA.
256 point fft/ifft - Overview :: Pipelined FFT/IFFT 256 points processor :: OpenCores
- FFT unit for 10 bit data and coefficients, and 2 data buffers occupies 1652 CLB slices, 4 DSP48 blocks, and 2,5 kbit of RAM in Xilinx XC4SX25 FPGA, and 670 CLB slices 4 DSP48E blocks, and 2,5 kbit of RAM in Xilinx XC5SX25 FPGA, data buffers are implemented on the distributed RAM.
OK the above listed resources are for a Xilinx FPGA, and not Altera FPGA used in the LimeSDR, but for simplicity sake if you consider each CLB (configurable logic block) as being a LAB (logic array block), you can see that a FFT does require a lot of resources, the question is how much free resources exist in the LimeSDR FPGA chips ?
LimeSDR-USB - EP4CE40F23C8N (Cyclone IV E 2475 LABs 39600 LE 1161216 RAM(bits) 328 IOs)
LimeSDR-PCIe - EP4CGX30CF23C7N (Cyclone IV GX 1840 LABs 29440 LE 1105920 RAM(bits) 290 IOs)
I’m sure that some public FFT core could be adapted and squeezed inside the existing FPGA, but I suspect that the FFT size for 12-bit samples would not be very big at all. I would love to be proven wrong though.