# FPGA to LMS I2C (Pin C17, C21)

**URL:** <https://discourse.myriadrf.org/t/fpga-to-lms-i2c-pin-c17-c21/1370>\
**Category:** Uncategorized\
**Created:** [22 June 2017 17:04 UTC](https://discourse.myriadrf.org/t/fpga-to-lms-i2c-pin-c17-c21/1370 "2017-06-22T17:04:07Z")\
**Posts on this page:** 6\
**Page:** 1

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**Author:** ![Sombrero](https://avatars.discourse-cdn.com/v4/letter/s/94ad74/32.png) [@Sombrero](https://discourse.myriadrf.org/u/Sombrero)\
**Post date:** [22 June 2017 17:04 UTC](https://discourse.myriadrf.org/t/fpga-to-lms-i2c-pin-c17-c21/1370/1 "2017-06-22T17:04:07Z")

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Hello guys,

we are currently looking into the FPGA and LMS connection. It seems like the I2C connection from the LMS7002M to the EEPROM’s is also connected to the FPGA. But if you look into the Gateware they are not used?

LMS **PIN C27** (I2C SCL) —\> FPGA **PIN C17**  
LMS **PIN D26** (I2C SDA) —\> FPGA **PIN C21**

**Schematic Screenshot:**

 ![](https://canada1.discourse-cdn.com/flex034/uploads/myriadrf/original/1X/3bf6bbe9f6248dd719bd322c8188fb8c54c47c54.png)

**PCB Screenshot (connected to the FPGA):**

 ![](https://canada1.discourse-cdn.com/flex034/uploads/myriadrf/original/1X/dc0169586de9c215daf4abbe7eddcc287b762515.png)

**Pin Planner (Quartus) Screenshot (C17, C21 not used):**

 ![](https://canada1.discourse-cdn.com/flex034/uploads/myriadrf/original/1X/09e7e8313565e3962e75efa447793464731874d0.png)

Did you tried to access the LMS EEPROM via the FPGA? We just want to make sure that no I2C connection between the FPGA and LMS is needed. However, they are physically connected even if the Gateware does not use the PIN’s C17 and C21.

Best regards  
Sombrero

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**Author:** ![andrewback](https://avatars.discourse-cdn.com/v4/letter/a/22d042/32.png) [@andrewback](https://discourse.myriadrf.org/u/andrewback)\
**Post date:** [23 June 2017 09:08 UTC](https://discourse.myriadrf.org/t/fpga-to-lms-i2c-pin-c17-c21/1370/2 "2017-06-23T09:08:08Z")

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Hi @Sombrero, this is probably one for @Zack.

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**Author:** ![Sombrero](https://avatars.discourse-cdn.com/v4/letter/s/94ad74/32.png) [@Sombrero](https://discourse.myriadrf.org/u/Sombrero)\
**Post date:** [23 June 2017 09:50 UTC](https://discourse.myriadrf.org/t/fpga-to-lms-i2c-pin-c17-c21/1370/3 "2017-06-23T09:50:15Z")

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Thank you @andrewback. Would be great to know whats happening there @Zack.  
It’s a great project and very active Discourse forum - keep it up guys! 🙂

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [23 June 2017 10:18 UTC](https://discourse.myriadrf.org/t/fpga-to-lms-i2c-pin-c17-c21/1370/4 "2017-06-23T10:18:18Z")

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Hi @Sombrero,

> [@Sombrero](#):
>
> Did you tried to access the LMS EEPROM via the FPGA? We just want to make sure that no I2C connection between the FPGA and LMS is needed. However, they are physically connected even if the Gateware does not use the PIN’s C17 and C21.

No need to connect I2C to FPGA. It is made for debugging purposes only.

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**Author:** ![Sombrero](https://avatars.discourse-cdn.com/v4/letter/s/94ad74/32.png) [@Sombrero](https://discourse.myriadrf.org/u/Sombrero)\
**Post date:** [23 June 2017 10:24 UTC](https://discourse.myriadrf.org/t/fpga-to-lms-i2c-pin-c17-c21/1370/5 "2017-06-23T10:24:43Z")

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That’s what I was hoping for, perfect thank you! The unexpected debugging capability actually helps us in our development.🙂  
Have a great weekend!

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**Author:** ![Zack](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/zack/32/89_2.png) [@Zack](https://discourse.myriadrf.org/u/Zack)\
**Post date:** [23 June 2017 10:26 UTC](https://discourse.myriadrf.org/t/fpga-to-lms-i2c-pin-c17-c21/1370/6 "2017-06-23T10:26:55Z")

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Excellent!

> [@Sombrero](#):
>
> Have a great weekend!

Same to you!