# FPGA Code not Compiling

**URL:** <https://discourse.myriadrf.org/t/fpga-code-not-compiling/7095>\
**Category:** LimeSDR\
**Created:** [19 April 2021 10:34 UTC](https://discourse.myriadrf.org/t/fpga-code-not-compiling/7095 "2021-04-19T10:34:34Z")\
**Posts on this page:** 1\
**Showing post:** 2

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**Author:** ![mzs](https://yyz2.discourse-cdn.com/flex034/user_avatar/discourse.myriadrf.org/mzs/32/2678_2.png) [@mzs](https://discourse.myriadrf.org/u/mzs)\
**Post date:** [19 April 2021 21:10 UTC](https://discourse.myriadrf.org/t/fpga-code-not-compiling/7095/2 "2021-04-19T21:10:18Z")

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Are you using the exact same version ([Altera Quartus prime 15.1 Lite Edition with Cyclone IV device support](https://github.com/myriadrf/LimeSDR-USB_GW/blob/master/doc/LimeSDR_USB_Gateware_Description_v01r01.pdf)) that was used for the gateware development ?

If you search, you’ll find that other people had similar problems attempting to use later versions.  
e.g.

> [@LimeSDR FPGA upgrade to EP4CE115F23C8 (?)](https://discourse.myriadrf.org/t/limesdr-fpga-upgrade-to-ep4ce115f23c8/1010/9):
>
> Just an update, I was able to synthesize the “original/unmodified” design successfully. I had an initial issue because I was running with a newer Quartus version. The issue was resolved when running with version 15.1.

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_[View the full topic](https://discourse.myriadrf.org/t/fpga-code-not-compiling/7095)._